Merge pull request #2 from rcore-os/merge-upstream

Merge upstream

Author: wangrunji0408

.travis.yml

@@ -7,11 +7,13 @@ env:
 rust:
   - nightly
   - stable
-  - 1.30.0 # MSRV
+  - 1.31.0 # MSRV
 
 if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
 
 matrix:
+  allow_failures:
+    - rust: nightly
   include:
     - env: TARGET=riscv64imac-unknown-none-elf
       rust: nightly
@@ -26,6 +28,10 @@ matrix:
       language: bash
       if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
 
+    - env: RUSTFMT=1
+      rust: stable
+      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
+
 
 install:
   - ci/install.sh
@@ -38,9 +44,6 @@ cache:
   cargo: true
   directories:
     - gcc
-before_cache:
-  # Travis can't cache files that are not readable by "others"
-  - chmod -R a+r $HOME/.cargo
 
 branches:
   only:

CHANGELOG.md

@@ -0,0 +1,37 @@
+# Change Log
+
+All notable changes to this project will be documented in this file.
+
+The format is based on [Keep a Changelog](http://keepachangelog.com/)
+and this project adheres to [Semantic Versioning](http://semver.org/).
+
+## [Unreleased]
+
+### Changed
+
+- Updated Minimum Supported Rust Version to 1.31.0
+- Use `llvm_asm!` instead of `asm!`
+
+## [v0.5.6] - 2020-03-14
+
+### Added
+
+- Added vexriscv-specific registers
+
+## [v0.5.5] - 2020-02-28
+
+### Added
+
+- Added `riscv32i-unknown-none-elf` target support
+- Added user trap setup and handling registers
+- Added write methods for the `mip` and `satp` registers
+- Added `mideleg` register
+- Added Changelog
+
+### Changed
+
+- Fixed MSRV by restricting the upper bound of `bare-metal` version
+
+[Unreleased]: https://github.com/rust-embedded/riscv/compare/v0.5.6...HEAD
+[v0.5.6]: https://github.com/rust-embedded/riscv/compare/v0.5.5...v0.5.6
+[v0.5.5]: https://github.com/rust-embedded/riscv/compare/v0.5.4...v0.5.5

CODE_OF_CONDUCT.md

@@ -2,15 +2,15 @@
 
 ## Conduct
 
-**Contact**: [RISCV team](https://github.com/rust-embedded/wg#the-riscv-team)
+**Contact**: [RISC-V team](https://github.com/rust-embedded/wg#the-riscv-team)
 
 * We are committed to providing a friendly, safe and welcoming environment for all, regardless of level of experience, gender identity and expression, sexual orientation, disability, personal appearance, body size, race, ethnicity, age, religion, nationality, or other similar characteristic.
 * On IRC, please avoid using overtly sexual nicknames or other nicknames that might detract from a friendly, safe and welcoming environment for all.
 * Please be kind and courteous. There's no need to be mean or rude.
 * Respect that people have differences of opinion and that every design or implementation choice carries a trade-off and numerous costs. There is seldom a right answer.
 * Please keep unstructured critique to a minimum. If you have solid ideas you want to experiment with, make a fork and see how it works.
 * We will exclude you from interaction if you insult, demean or harass anyone. That is not welcome behavior. We interpret the term "harassment" as including the definition in the [Citizen Code of Conduct](http://citizencodeofconduct.org/); if you have any lack of clarity about what might be included in that concept, please read their definition. In particular, we don't tolerate behavior that excludes people in socially marginalized groups.
-* Private harassment is also unacceptable. No matter who you are, if you feel you have been or are being harassed or made uncomfortable by a community member, please contact one of the channel ops or any of the [RISCV team][team] immediately. Whether you're a regular contributor or a newcomer, we care about making this community a safe place for you and we've got your back.
+* Private harassment is also unacceptable. No matter who you are, if you feel you have been or are being harassed or made uncomfortable by a community member, please contact one of the channel ops or any of the [RISC-V team][team] immediately. Whether you're a regular contributor or a newcomer, we care about making this community a safe place for you and we've got your back.
 * Likewise any spamming, trolling, flaming, baiting or other attention-stealing behavior is not welcome.
 
 ## Moderation

Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "riscv"
-version = "0.5.0"
+version = "0.5.6"
 repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <[email protected]>"]
 categories = ["embedded", "hardware-support", "no-std"]
@@ -9,10 +9,12 @@ keywords = ["riscv", "register", "peripheral"]
 license = "ISC"
 
 [dependencies]
-bare-metal = "0.2.0"
+bare-metal = "0.2.5"
 bitflags = "1.0"
-bit_field = "0.9.0"
-log = "0.4"
+bit_field = "0.10.0"
+
+[build-dependencies]
+riscv-target = "0.1.2"
 
 [features]
-inline-asm = []
+inline-asm = []

README.md

@@ -4,15 +4,20 @@
 
 # `riscv`
 
-> Low level access to RISCV processors
+> Low level access to RISC-V processors
 
-This project is developed and maintained by the [RISCV team][team].
+This project is developed and maintained by the [RISC-V team][team].
 
 ## [Documentation](https://docs.rs/crate/riscv)
 
+## Minimum Supported Rust Version (MSRV)
+
+This crate is guaranteed to compile on stable Rust 1.31.0 and up. It *might*
+compile with older versions but that may change in any new patch release.
+
 ## License
 
-Copyright 2018 [RISCV team][team]
+Copyright 2019 [RISC-V team][team]
 
 Permission to use, copy, modify, and/or distribute this software for any purpose
 with or without fee is hereby granted, provided that the above copyright notice
@@ -29,7 +34,7 @@ THIS SOFTWARE.
 ## Code of Conduct
 
 Contribution to this crate is organized under the terms of the [Rust Code of
-Conduct][CoC], the maintainer of this crate, the [RISCV team][team], promises
+Conduct][CoC], the maintainer of this crate, the [RISC-V team][team], promises
 to intervene to uphold that code of conduct.
 
 [CoC]: CODE_OF_CONDUCT.md