Late timings

Sinclair ZX Spectrum 16K/48K models

The INT signal begins 1 T-state earlier if /RFSH is low during the T-state preceding the one in which the INT signal would normally begin. If interrupts are enabled, this causes instructions whose last M-cycle is an opcode fetch of 4 T-states ending 14,338 T-states before the first VRAM pixel to be immediately followed by the INT response, which then starts 14,337 T-states before the first VRAM pixel.

The details of this behavior were uncovered by Marta Sevillano Mancilla (aka MartianGirl and TheMartian) in May 2025. Weiv reportedly emulated this behavior some time earlier, but never shared an explanation of how it worked with the community.

Please note that the state of the /RFSH line may not be related to the actual cause of this behavior, but it is useful to describe the conditions under which late timings occur. Additionally, This behavior is temperature-dependent: some machines tend to exhibit late timings when cold and shift to early timings as they warm up.

Sinclair ZX Spectrum +128K and +2 models

The INT signal begins 1 T-state earlier. This is common on ZX Spectrum +2 (grey) models. ZX Spectrum +128K (toastrack) models can also exhibit this behavior occasionally, possibly due to temperature.