pcie_7x

PCIe Endpoint on Xilinx 7-Series FPGAs using the PCIE_2_1 hard block and GTP/GTX transceivers. No proprietary Vivado IP cores! Compatible with openXC7!

Clock Structure

src/pipe_clock.v generates all the clocks.

                          +-------------+
(PCIe refclk) sys_clk_p>--| IBUFDS_GTE2 |
100 MHz       sys_clk_n>--|             |--> sys_clk --> Goes to GTPE2_COMMON
                          +-------------+
                         
(from GTPE2_CHANNEL) +------+                    BUFG
TXOUTCLK ---|>-------| MMCM |-->125 MHz-----------|>---+--DCLK (dynamic reconfig)
100 MHz    BUFG      |      |                   BUFGCTRL
                     |      |-->125 MHz-Gen1------+\___+--RXUSRCLK (clk for RX data)                             
                     |      |-->250 MHz-Gen2------+/   +--OOBCLK (out of bond)
                     |      |                          +--PCLK (main PCIe logic)
                     |      |-->user1* 
                     |      |-->user2* 
                     +------+
                                   *usually 62.5 MHz/125 MHz for Gen1/Gen2

Module Structure

src/pipe_wrapper.v contains the GTP transceiver. It's connected to the PCIE_2_1 src/pcie_block.v via the PIPE interface. PCIE_2_1 handles from upper physical layer, data link layer, up to transaction layer.

 To User Design                                                         To PCIe Lane
                     +---------------+  PIPE interface +---------------+ TX pair
AXIS TX/RX  +------+ |  PCIE_2_1     |-------/---------| GTPE2_CHANNEL |------/-----
=/==========| TRN2 |=|  Hard Block   |                 |               |------/-----
=/==========| AXIS |=|               |              +--|               | RX pair
            +------+ |               |              |  +---------------+ CLK pair
-/-------------------|               |              |+--| GTPE2_COMMON |------/-----
Configs              +---------------+              ||  |              |
                     |  RX   |  TX   |              ||  +--------------+
                     | BRAMS | BRAMS |              ||
                     +---------------+             +-------+
Reset                                              | Reset |
---------------------------------------------------|       |
                                                   +-------+

For PCIE_2_1 parameters and port definitions, please refer to UG477.

Supported FPGAs and Modes

PCIe Gen1 x1, PCIe Gen2 x1 on AMD/Xilinx Artix 7 and Kintex 7

Supported Boards

Alinx AC7100B SoM (Artix 7 100t), Wavelet uSDR (Artix 7 35t), YPCB (Kintex 7 480t), HVS (Kintex 7 70t)

Tested Hosts

AMD 3700X on B450m (All boards)

Intel i3 13th Gen on B760m (Wavelet uSDR with base board)

Raspberry Pi 5 (Wavelet uSDR in M.2 mode, YPCB Kintex 7 480t with M.2 converter and external power supply)

Bitstream with openXC7 quickstart!

docker run -it --rm -v .:/mnt regymm/openxc7 make -C /mnt -f Makefile.alinx_100t.openxc7

Documentation

Build and run: Artix 7 PCIe

PCIe Gen2 / board without reset: uSDR Guide

MSI interrupt / kernel driver: MSI Interrupt

Standard PCIe cards on Raspberry Pi: YPCB_Kintex7_RPi5

Funding

This project is funded through NGI0 Entrust, a fund established by NLnet with financial support from the European Commission's Next Generation Internet program. Learn more at the NLnet project page.