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soc: arm: Add initial support for RA8M1 SOC series
Add minimal support for RA8M1 SOC series. Signed-off-by: Duy Nguyen <[email protected]> Signed-off-by: Quy Tran <[email protected]>
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‎dts/arm/renesas/ra/ra8/r7fa8m1ahecbd.dtsi‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/renesas/ra/ra8/r7fa8m1xh.dtsi>
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#include <zephyr/dt-bindings/clock/ra_clock.h>
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/ {
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clocks {
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xtal: clock-xtal {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(20)>;
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#clock-cells = <0>;
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};
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hoco: clock-hoco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(48)>;
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#clock-cells = <0>;
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};
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moco: clock-moco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(8)>;
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#clock-cells = <0>;
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};
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loco: clock-loco {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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subclk: clock-subclk {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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clock: clock {
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compatible = "renesas,ra8m1-clock";
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#clock-cells = <0>;
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/* PLL */
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pll-source = <RA_PLL_SOURCE_MAIN_OSC>;
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pll-div = <RA_PLL_DIV_1>;
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pll-mul = <48 0>;
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pll-divp = <RA_PLL_DIV_2>;
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pll-freqp = <DT_FREQ_M(480)>;
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pll-divq = <RA_PLL_DIV_2>;
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pll-freqq = <DT_FREQ_M(480)>;
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pll-divr = <RA_PLL_DIV_2>;
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pll-freqr = <DT_FREQ_M(480)>;
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/* PLL2 */
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pll2-source = <RA_PLL_SOURCE_DISABLE>;
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pll2-div = <RA_PLL_DIV_1>;
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pll2-mul = <48 0>;
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pll2-divp = <RA_PLL_DIV_2>;
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pll2-freqp = <DT_FREQ_M(0)>;
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pll2-divq = <RA_PLL_DIV_2>;
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pll2-freqq = <DT_FREQ_M(0)>;
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pll2-divr = <RA_PLL_DIV_2>;
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pll2-freqr = <DT_FREQ_M(0)>;
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/* System Clock */
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sysclock-source = <RA_CLOCK_SOURCE_PLL1P>;
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cpuclk-div = <RA_SYS_CLOCK_DIV_1>;
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iclk-div = <RA_SYS_CLOCK_DIV_2>;
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pclka-div = <RA_SYS_CLOCK_DIV_4>;
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pclkb-div = <RA_SYS_CLOCK_DIV_8>;
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pclkc-div = <RA_SYS_CLOCK_DIV_8>;
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pclkd-div = <RA_SYS_CLOCK_DIV_4>;
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pclke-div = <RA_SYS_CLOCK_DIV_2>;
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bclk-div = <RA_SYS_CLOCK_DIV_4>;
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bclk-out = <2>;
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fclk-div = <RA_SYS_CLOCK_DIV_8>;
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sdclk-out = <1>;
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uclk-source = <RA_CLOCK_SOURCE_DISABLE>;
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uclk-div = <RA_USB_CLOCK_DIV_5>;
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u60clk-source = <RA_CLOCK_SOURCE_DISABLE>;
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u60clk-div = <RA_USB60_CLOCK_DIV_5>;
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octaspiclk-source = <RA_CLOCK_SOURCE_DISABLE>;
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octaspiclk-div = <RA_OCTA_CLOCK_DIV_4>;
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canfdclk-source = <RA_CLOCK_SOURCE_DISABLE>;
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canfdclk-div = <RA_CANFD_CLOCK_DIV_8>;
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clkout-source = <RA_PLL_SOURCE_LOCO>;
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clkout-div = <RA_SYS_CLOCK_DIV_1>;
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sciclk-source = <RA_CLOCK_SOURCE_DISABLE>;
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sciclk-div = <RA_SCI_CLOCK_DIV_4>;
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spiclk-source = <RA_CLOCK_SOURCE_DISABLE>;
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spiclk-div = <RA_SPI_CLOCK_DIV_4>;
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i3cclk-source = <RA_CLOCK_SOURCE_DISABLE>;
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i3cclk-div = <RA_I3C_CLOCK_DIV_3>;
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};
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};
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};

‎dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/renesas/ra/ra8/ra8x1.dtsi>

‎dts/arm/renesas/ra/ra8/ra8x1.dtsi‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv8.1-m.dtsi>
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#include <freq.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m85";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8.1m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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};
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soc {
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sram0: memory@22000000 {
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compatible = "mmio-sram";
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reg = <0x22000000 DT_SIZE_K(896)>;
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};
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system: system@4001e000 {
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compatible = "renesas,ra-system";
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reg = <0x4001e000 0x1000>;
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status = "okay";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};

‎dts/bindings/clock/renesas,ra8m1-clock.yaml‎

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: Renesas RA8M1 Clock Generation Circuit
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compatible: "renesas,ra8m1-clock"
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include: [clock-controller.yaml, base.yaml]
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properties:
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pll-source:
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type: int
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required: true
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pll-div:
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type: int
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required: true
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pll-mul:
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type: array
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required: true
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pll-divp:
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type: int
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required: true
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pll-freqp:
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type: int
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required: true
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pll-divq:
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type: int
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required: true
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pll-freqq:
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type: int
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required: true
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pll-divr:
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type: int
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required: true
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pll-freqr:
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type: int
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required: true
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pll2-source:
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type: int
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required: true
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pll2-div:
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type: int
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required: true
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pll2-mul:
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type: array
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required: true
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pll2-divp:
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type: int
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required: true
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pll2-freqp:
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type: int
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required: true
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pll2-divq:
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type: int
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required: true
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pll2-freqq:
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type: int
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required: true
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pll2-divr:
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type: int
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required: true
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pll2-freqr:
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type: int
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required: true
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sysclock-source:
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type: int
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required: true
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cpuclk-div:
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type: int
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required: true
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iclk-div:
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type: int
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required: true
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pclka-div:
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type: int
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required: true
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pclkb-div:
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type: int
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required: true
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pclkc-div:
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type: int
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required: true
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pclkd-div:
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type: int
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required: true
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pclke-div:
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type: int
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required: true
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bclk-div:
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type: int
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required: true
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bclk-out:
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type: int
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required: true
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fclk-div:
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type: int
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required: true
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sdclk-out:
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type: int
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required: true
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uclk-source:
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type: int
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required: true
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uclk-div:
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type: int
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required: true
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u60clk-source:
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type: int
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required: true
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u60clk-div:
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type: int
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required: true
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octaspiclk-source:
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type: int
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required: true
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octaspiclk-div:
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type: int
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required: true
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canfdclk-source:
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type: int
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required: true
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canfdclk-div:
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type: int
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required: true
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clkout-source:
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type: int
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required: true
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clkout-div:
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type: int
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required: true
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sciclk-source:
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type: int
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required: true
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sciclk-div:
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type: int
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required: true
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spiclk-source:
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type: int
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required: true
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spiclk-div:
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type: int
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required: true
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i3cclk-source:
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type: int
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required: true
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i3cclk-div:
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type: int
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required: true

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