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target: cortex-m: add support for armv8m caches
Cores like Cortex-M7, Cortex-M55 and Cortex-M85 can have either D-Cache and/or I-Cache. Using SW breakpoints in RAM requires handling these caches. Detect the presence of cache at examine. Detect cache state (enable/disable) at debug entry. Take care of caches synchronization through the PoC (usually the SRAM) while setting and removing SW breakpoints. Add command 'cache_info' to check cache presence and size. Change-Id: Ice637c215fe3042c8fff57edefbab1b86515ef4b Signed-off-by: Antonio Borneo <[email protected]> Reviewed-on: https://review.openocd.org/c/openocd/+/9077 Reviewed-by: Tomas Vanek <[email protected]> Tested-by: jenkins
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‎doc/openocd.texi‎

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@@ -11120,6 +11120,10 @@ Enable or disable trace output for all ITM stimulus ports.
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@subsection Cortex-M specific commands
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@cindex Cortex-M
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@deffn {Command} {cortex_m cache_info}
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Report information about the type and size of the cache, if present.
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@end deffn
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@deffn {Command} {cortex_m maskisr} (@option{auto}|@option{on}|@option{off}|@option{steponly})
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Control masking (disabling) interrupts during target step/resume.
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‎src/target/Makefile.am‎

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@@ -75,6 +75,7 @@ ARMV6_SRC = \
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ARMV7_SRC = \
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%D%/armv7m.c \
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%D%/armv7m_cache.c \
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%D%/armv7m_trace.c \
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%D%/cortex_m.c \
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%D%/armv7a.c \
@@ -183,6 +184,7 @@ ARC_SRC = \
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%D%/armv4_5_cache.h \
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%D%/armv7a.h \
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%D%/armv7m.h \
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%D%/armv7m_cache.h \
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%D%/armv7m_trace.h \
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%D%/armv8.h \
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%D%/armv8_dpm.h \

‎src/target/armv7m.h‎

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#define OPENOCD_TARGET_ARMV7M_H
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#include "arm.h"
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#include "armv7m_cache.h"
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#include "armv7m_trace.h"
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struct adiv5_ap;
@@ -239,6 +240,8 @@ struct armv7m_common {
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/* hla_target uses a high level adapter that does not support all functions */
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bool is_hla_target;
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struct armv7m_cache_common armv7m_cache;
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struct armv7m_trace_config trace_config;
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/* Direct processor core register read and writes */

‎src/target/armv7m_cache.c‎

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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2025 by STMicroelectronics
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* Copyright (C) 2025 by Antonio Borneo <[email protected]>
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <stdint.h>
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#include <helper/align.h>
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#include <helper/bitfield.h>
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#include <helper/bits.h>
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#include <helper/command.h>
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#include <helper/log.h>
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#include <helper/types.h>
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#include <target/arm_adi_v5.h>
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#include <target/armv7m_cache.h>
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#include <target/cortex_m.h>
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static int get_cache_info(struct adiv5_ap *ap, unsigned int cl,
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unsigned int ind, uint32_t *ccsidr)
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{
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uint32_t csselr = FIELD_PREP(CSSELR_LEVEL_MASK, cl)
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| FIELD_PREP(CSSELR_IND_MASK, ind);
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int retval = mem_ap_write_u32(ap, CSSELR, csselr);
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if (retval != ERROR_OK)
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return retval;
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return mem_ap_read_u32(ap, CCSIDR, ccsidr);
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}
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static int get_d_u_cache_info(struct adiv5_ap *ap, unsigned int cl,
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uint32_t *ccsidr)
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{
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return get_cache_info(ap, cl, CSSELR_IND_DATA_OR_UNIFIED_CACHE, ccsidr);
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}
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static int get_i_cache_info(struct adiv5_ap *ap, unsigned int cl,
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uint32_t *ccsidr)
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{
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return get_cache_info(ap, cl, CSSELR_IND_INSTRUCTION_CACHE, ccsidr);
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}
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static struct armv7m_cache_size decode_ccsidr(uint32_t ccsidr)
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{
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struct armv7m_cache_size size;
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size.line_len = 16 << FIELD_GET(CCSIDR_LINESIZE_MASK, ccsidr);
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size.associativity = FIELD_GET(CCSIDR_ASSOCIATIVITY_MASK, ccsidr) + 1;
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size.num_sets = FIELD_GET(CCSIDR_NUMSETS_MASK, ccsidr) + 1;
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size.cache_size = size.line_len * size.associativity * size.num_sets / 1024;
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// compute info for set way operation on cache
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size.index_shift = FIELD_GET(CCSIDR_LINESIZE_MASK, ccsidr) + 2;
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size.index = FIELD_GET(CCSIDR_NUMSETS_MASK, ccsidr);
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size.way = FIELD_GET(CCSIDR_ASSOCIATIVITY_MASK, ccsidr);
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unsigned int i = 0;
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while (((size.way << i) & 0x80000000) == 0)
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i++;
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size.way_shift = i;
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return size;
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}
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int armv7m_identify_cache(struct target *target)
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{
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struct armv7m_common *armv7m = target_to_armv7m(target);
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struct armv7m_cache_common *cache = &armv7m->armv7m_cache;
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uint32_t clidr;
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int retval = mem_ap_read_u32(armv7m->debug_ap, CLIDR, &clidr);
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if (retval != ERROR_OK)
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return retval;
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uint32_t ctr;
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retval = mem_ap_read_u32(armv7m->debug_ap, CTR, &ctr);
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if (retval != ERROR_OK)
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return retval;
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// retrieve selected cache for later restore
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uint32_t csselr;
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retval = mem_ap_read_atomic_u32(armv7m->debug_ap, CSSELR, &csselr);
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if (retval != ERROR_OK)
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return retval;
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if (clidr == 0) {
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LOG_TARGET_DEBUG(target, "No cache detected");
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return ERROR_OK;
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}
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if (FIELD_GET(CTR_FORMAT_MASK, ctr) != CTR_FORMAT_PROVIDED) {
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LOG_ERROR("Wrong value in CTR register");
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return ERROR_FAIL;
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}
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cache->i_min_line_len = 4UL << FIELD_GET(CTR_IMINLINE_MASK, ctr);
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cache->d_min_line_len = 4UL << FIELD_GET(CTR_DMINLINE_MASK, ctr);
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LOG_TARGET_DEBUG(target,
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"ctr=0x%" PRIx32 " ctr.i_min_line_len=%" PRIu32 " ctr.d_min_line_len=%" PRIu32,
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ctr, cache->i_min_line_len, cache->d_min_line_len);
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cache->loc = FIELD_GET(CLIDR_LOC_MASK, clidr);
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LOG_TARGET_DEBUG(target,
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"clidr=0x%" PRIx32 " Number of cache levels to PoC=%" PRIu32,
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clidr, cache->loc);
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// retrieve all available inner caches
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uint32_t d_u_ccsidr[8], i_ccsidr[8];
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for (unsigned int cl = 0; cl < cache->loc; cl++) {
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unsigned int ctype = FIELD_GET(CLIDR_CTYPE_MASK(cl + 1), clidr);
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// skip reserved values
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if (ctype > CLIDR_CTYPE_UNIFIED_CACHE)
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continue;
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cache->arch[cl].ctype = ctype;
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// separate d or unified d/i cache at this level ?
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if (ctype & (CLIDR_CTYPE_UNIFIED_CACHE | CLIDR_CTYPE_D_CACHE)) {
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// retrieve d-cache info
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retval = get_d_u_cache_info(armv7m->debug_ap, cl, &d_u_ccsidr[cl]);
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if (retval != ERROR_OK)
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break;
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}
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if (ctype & CLIDR_CTYPE_I_CACHE) {
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// retrieve i-cache info
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retval = get_i_cache_info(armv7m->debug_ap, cl, &i_ccsidr[cl]);
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if (retval != ERROR_OK)
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break;
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}
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}
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// restore selected cache
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int retval1 = mem_ap_write_atomic_u32(armv7m->debug_ap, CSSELR, csselr);
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if (retval != ERROR_OK)
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return retval;
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if (retval1 != ERROR_OK)
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return retval1;
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for (unsigned int cl = 0; cl < cache->loc; cl++) {
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unsigned int ctype = cache->arch[cl].ctype;
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// separate d or unified d/i cache at this level ?
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if (ctype & (CLIDR_CTYPE_UNIFIED_CACHE | CLIDR_CTYPE_D_CACHE)) {
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cache->has_d_u_cache = true;
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cache->arch[cl].d_u_size = decode_ccsidr(d_u_ccsidr[cl]);
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LOG_TARGET_DEBUG(target,
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"data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
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cache->arch[cl].d_u_size.index,
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cache->arch[cl].d_u_size.index_shift,
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cache->arch[cl].d_u_size.way,
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cache->arch[cl].d_u_size.way_shift);
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LOG_TARGET_DEBUG(target,
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"cache line %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
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cache->arch[cl].d_u_size.line_len,
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cache->arch[cl].d_u_size.cache_size,
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cache->arch[cl].d_u_size.associativity);
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}
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if (ctype & CLIDR_CTYPE_I_CACHE) {
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cache->has_i_cache = true;
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cache->arch[cl].i_size = decode_ccsidr(i_ccsidr[cl]);
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LOG_TARGET_DEBUG(target,
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"instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
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cache->arch[cl].i_size.index,
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cache->arch[cl].i_size.index_shift,
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cache->arch[cl].i_size.way,
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cache->arch[cl].i_size.way_shift);
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LOG_TARGET_DEBUG(target,
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"cache line %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
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cache->arch[cl].i_size.line_len,
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cache->arch[cl].i_size.cache_size,
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cache->arch[cl].i_size.associativity);
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}
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}
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cache->info_valid = true;
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return ERROR_OK;
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}
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int armv7m_d_cache_flush(struct target *target, uint32_t address,
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unsigned int length)
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{
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struct armv7m_common *armv7m = target_to_armv7m(target);
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struct armv7m_cache_common *cache = &armv7m->armv7m_cache;
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if (!cache->info_valid || !cache->has_d_u_cache)
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return ERROR_OK;
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uint32_t line_len = cache->d_min_line_len;
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uint32_t addr_line = ALIGN_DOWN(address, line_len);
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uint32_t addr_end = address + length;
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while (addr_line < addr_end) {
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int retval = mem_ap_write_u32(armv7m->debug_ap, DCCIMVAC, addr_line);
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if (retval != ERROR_OK)
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return retval;
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addr_line += line_len;
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keep_alive();
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}
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return dap_run(armv7m->debug_ap->dap);
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}
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int armv7m_i_cache_inval(struct target *target, uint32_t address,
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unsigned int length)
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{
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struct armv7m_common *armv7m = target_to_armv7m(target);
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struct armv7m_cache_common *cache = &armv7m->armv7m_cache;
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if (!cache->info_valid || !cache->has_i_cache)
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return ERROR_OK;
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uint32_t line_len = cache->i_min_line_len;
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uint32_t addr_line = ALIGN_DOWN(address, line_len);
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uint32_t addr_end = address + length;
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while (addr_line < addr_end) {
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int retval = mem_ap_write_u32(armv7m->debug_ap, ICIMVAU, addr_line);
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if (retval != ERROR_OK)
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return retval;
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addr_line += line_len;
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keep_alive();
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}
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return dap_run(armv7m->debug_ap->dap);
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}
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int armv7m_handle_cache_info_command(struct command_invocation *cmd,
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struct target *target)
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{
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struct armv7m_common *armv7m = target_to_armv7m(target);
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struct armv7m_cache_common *cache = &armv7m->armv7m_cache;
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if (!target_was_examined(target)) {
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command_print(cmd, "Target not examined yet");
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return ERROR_FAIL;
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}
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if (!cache->info_valid) {
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command_print(cmd, "No cache detected");
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return ERROR_OK;
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}
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for (unsigned int cl = 0; cl < cache->loc; cl++) {
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struct armv7m_arch_cache *arch = &cache->arch[cl];
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if (arch->ctype & CLIDR_CTYPE_I_CACHE)
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command_print(cmd,
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"L%d I-Cache: line length %" PRIu32 ", associativity %" PRIu32
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", num sets %" PRIu32 ", cache size %" PRIu32 " KBytes",
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cl + 1,
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arch->i_size.line_len,
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arch->i_size.associativity,
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arch->i_size.num_sets,
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arch->i_size.cache_size);
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if (arch->ctype & (CLIDR_CTYPE_UNIFIED_CACHE | CLIDR_CTYPE_D_CACHE))
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command_print(cmd,
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"L%d %c-Cache: line length %" PRIu32 ", associativity %" PRIu32
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", num sets %" PRIu32 ", cache size %" PRIu32 " KBytes",
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cl + 1,
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(arch->ctype & CLIDR_CTYPE_D_CACHE) ? 'D' : 'U',
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arch->d_u_size.line_len,
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arch->d_u_size.associativity,
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arch->d_u_size.num_sets,
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arch->d_u_size.cache_size);
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}
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return ERROR_OK;
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}

‎src/target/armv7m_cache.h‎

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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2025 by STMicroelectronics
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* Copyright (C) 2025 by Antonio Borneo <[email protected]>
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*/
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#ifndef OPENOCD_TARGET_ARMV7M_CACHE_H
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#define OPENOCD_TARGET_ARMV7M_CACHE_H
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#include <stdbool.h>
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#include <stdint.h>
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#include <helper/types.h>
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struct target;
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struct armv7m_cache_size {
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// cache dimensioning
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uint32_t line_len;
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uint32_t associativity;
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uint32_t num_sets;
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uint32_t cache_size;
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// info for set way operation on cache
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uint32_t index;
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uint32_t index_shift;
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uint32_t way;
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uint32_t way_shift;
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};
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// information about one architecture cache at any level
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struct armv7m_arch_cache {
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unsigned int ctype; // cache type, CLIDR encoding
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struct armv7m_cache_size d_u_size; // data cache
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struct armv7m_cache_size i_size; // instruction cache
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};
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// common cache information
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struct armv7m_cache_common {
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bool info_valid;
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bool has_i_cache;
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bool has_d_u_cache;
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unsigned int loc; // level of coherency
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uint32_t d_min_line_len; // minimum d-cache line_len
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uint32_t i_min_line_len; // minimum i-cache line_len
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struct armv7m_arch_cache arch[6]; // cache info, L1 - L7
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};
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int armv7m_identify_cache(struct target *target);
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int armv7m_d_cache_flush(struct target *target, uint32_t address,
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unsigned int length);
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int armv7m_i_cache_inval(struct target *target, uint32_t address,
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unsigned int length);
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int armv7m_handle_cache_info_command(struct command_invocation *cmd,
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struct target *target);
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#endif /* OPENOCD_TARGET_ARMV7M_CACHE_H */

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