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Support for RISC-V RNMI registers

Status: Open.

#1320 In riscv-collab/riscv-openocd;

· kubeqz opened on Feb 13, 2026

Implement DMI behind Coresight DAP

Status: Open.

#1318 In riscv-collab/riscv-openocd;

· summershrimp opened on Jan 7, 2026

dcsr.stepie is default to zero although openocd set_maskisr is off

Status: Open.

#1317 In riscv-collab/riscv-openocd;

· fanghuaqi opened on Dec 31, 2025

Check the value read from target before performing address arithmetic based on it

Status: Open.

#1311 In riscv-collab/riscv-openocd;

· en-sc opened on Nov 5, 2025

Drop RTI cycle in case DMI delay is zero

Status: Open.

#1310 In riscv-collab/riscv-openocd;

· en-sc opened on Nov 5, 2025

Assertion failure when force-reading a dirty register

Status: Open.

#1309 In riscv-collab/riscv-openocd;

· en-sc opened on Nov 5, 2025

No need for busy delays after a DMI NOP.

Status: Open.

#1308 In riscv-collab/riscv-openocd;

· en-sc opened on Nov 5, 2025

DMI busy is mishandled on Microchip PolarFire SoC

Status: Open.

#1307 In riscv-collab/riscv-openocd;

· en-sc opened on Nov 5, 2025

Memory burst writes with abstractauto can fail due to missing BUSY checks

Status: Open.

#1306 In riscv-collab/riscv-openocd;

· nadime15 opened on Nov 4, 2025

OpenOCD incorrectly attempts to write to read-only vector CSRs (vl, vtype, vlenb)

Status: Open.

#1305 In riscv-collab/riscv-openocd;

· nadime15 opened on Nov 4, 2025

Drop the use of has_sufficient_progbuf() with riscv_program_exec()

Status: Open.

#1301 In riscv-collab/riscv-openocd;

· en-sc opened on Oct 27, 2025

Update misa register when hart halted

Status: Open.

#1298 In riscv-collab/riscv-openocd;

· lz-bro opened on Oct 13, 2025