Implement DMI behind Coresight DAP

[summershrimp]

Hi,

according to some document and real chip, some manufactor have DMI behind Coresight DAP design.

JTAG/SWD -> SWJ-DP -> APB-AP -> DMI registers
or
JTAG/SWD -> SWJ-DP -> AHB-AP -> DMI registers

It would be so nice if we can implement this feature to support more risc-v chips.

[1] https://kb.segger.com/J-Link_RISC-V#RISC-V_behind_a_CoreSight_DAP
[2] https://repo.lauterbach.com/pdfnew/debugger_riscv.pdf, Page 68.

[en-sc]

Please, see #1000

[summershrimp]

Actually it is not the same. #1000 is dap->jtag-ap->dtm->dm, our scenario is dap->mem_ap->dm, access memory through mem_ap to access dm registers.

[summershrimp]

find an implementation here:
tom-van/openocd-rp2350-riscv@a50b4cf