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flash: nor: ath79: fix build failure due to recent MIPS changes
Change-Id: I7139b0658f048afea2d16216c93e8946356a630d Signed-off-by: Paul Fertser <[email protected]> Reviewed-on: http://openocd.zylin.com/4151 Tested-by: jenkins Reviewed-by: Salvador Arroyo <[email protected]>
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‎src/flash/nor/ath79.c‎

Lines changed: 35 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -136,9 +136,9 @@ static int ath79_spi_bitbang_codegen(struct ath79_flash_bank *ath79_info,
136136

137137
const uint32_t preamble1[] = {
138138
/* $15 = MIPS32_PRACC_BASE_ADDR */
139-
MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR),
139+
MIPS32_LUI(0, 15, PRACC_UPPER_BASE_ADDR),
140140
/* $1 = io_base */
141-
MIPS32_LUI(1, UPPER16(io_base)),
141+
MIPS32_LUI(0, 1, UPPER16(io_base)),
142142
};
143143
ath79_pracc_addn(ctx, preamble1, ARRAY_SIZE(preamble1));
144144
if (ath79_info->spi.pre_deselect) {
@@ -148,31 +148,31 @@ static int ath79_spi_bitbang_codegen(struct ath79_flash_bank *ath79_info,
148148
ath79_info->spi.pre_deselect = 0;
149149
const uint32_t pre_deselect[] = {
150150
/* [$1 + FS] = 1 (enable flash io register access) */
151-
MIPS32_LUI(2, UPPER16(1)),
152-
MIPS32_ORI(2, 2, LOWER16(1)),
153-
MIPS32_SW(2, ATH79_REG_FS, 1),
151+
MIPS32_LUI(0, 2, UPPER16(1)),
152+
MIPS32_ORI(0, 2, 2, LOWER16(1)),
153+
MIPS32_SW(0, 2, ATH79_REG_FS, 1),
154154
/* deselect flash just in case */
155155
/* $2 = SPI_CS_DIS */
156-
MIPS32_LUI(2, UPPER16(cs_high)),
157-
MIPS32_ORI(2, 2, LOWER16(cs_high)),
156+
MIPS32_LUI(0, 2, UPPER16(cs_high)),
157+
MIPS32_ORI(0, 2, 2, LOWER16(cs_high)),
158158
/* [$1 + WRITE] = $2 */
159-
MIPS32_SW(2, ATH79_REG_WRITE, 1),
159+
MIPS32_SW(0, 2, ATH79_REG_WRITE, 1),
160160
};
161161
ath79_pracc_addn(ctx, pre_deselect, ARRAY_SIZE(pre_deselect));
162162
}
163163
const uint32_t preamble2[] = {
164164
/* t0 = CLOCK_LOW + 0-bit */
165-
MIPS32_LUI(8, UPPER16((clock_low + 0))),
166-
MIPS32_ORI(8, 8, LOWER16((clock_low + 0))),
165+
MIPS32_LUI(0, 8, UPPER16((clock_low + 0))),
166+
MIPS32_ORI(0, 8, 8, LOWER16((clock_low + 0))),
167167
/* t1 = CLOCK_LOW + 1-bit */
168-
MIPS32_LUI(9, UPPER16((clock_low + 1))),
169-
MIPS32_ORI(9, 9, LOWER16((clock_low + 1))),
168+
MIPS32_LUI(0, 9, UPPER16((clock_low + 1))),
169+
MIPS32_ORI(0, 9, 9, LOWER16((clock_low + 1))),
170170
/* t2 = CLOCK_HIGH + 0-bit */
171-
MIPS32_LUI(10, UPPER16((clock_high + 0))),
172-
MIPS32_ORI(10, 10, LOWER16((clock_high + 0))),
171+
MIPS32_LUI(0, 10, UPPER16((clock_high + 0))),
172+
MIPS32_ORI(0, 10, 10, LOWER16((clock_high + 0))),
173173
/* t3 = CLOCK_HIGH + 1-bit */
174-
MIPS32_LUI(11, UPPER16((clock_high + 1))),
175-
MIPS32_ORI(11, 11, LOWER16((clock_high + 1))),
174+
MIPS32_LUI(0, 11, UPPER16((clock_high + 1))),
175+
MIPS32_ORI(0, 11, 11, LOWER16((clock_high + 1))),
176176
};
177177
ath79_pracc_addn(ctx, preamble2, ARRAY_SIZE(preamble2));
178178

@@ -186,58 +186,58 @@ static int ath79_spi_bitbang_codegen(struct ath79_flash_bank *ath79_info,
186186
if (bit) {
187187
/* [$1 + WRITE] = t1 */
188188
pracc_add(ctx, 0,
189-
MIPS32_SW(9, ATH79_REG_WRITE, 1));
189+
MIPS32_SW(0, 9, ATH79_REG_WRITE, 1));
190190
/* [$1 + WRITE] = t3 */
191191
pracc_add(ctx, 0,
192-
MIPS32_SW(11, ATH79_REG_WRITE, 1));
192+
MIPS32_SW(0, 11, ATH79_REG_WRITE, 1));
193193
} else {
194194
/* [$1 + WRITE] = t0 */
195195
pracc_add(ctx, 0,
196-
MIPS32_SW(8, ATH79_REG_WRITE, 1));
196+
MIPS32_SW(0, 8, ATH79_REG_WRITE, 1));
197197
/* [$1 + WRITE] = t2 */
198198
pracc_add(ctx, 0,
199-
MIPS32_SW(10, ATH79_REG_WRITE, 1));
199+
MIPS32_SW(0, 10, ATH79_REG_WRITE, 1));
200200
}
201201
}
202202
if (i % 4 == 3) {
203203
/* $3 = [$1 + DATA] */
204-
pracc_add(ctx, 0, MIPS32_LW(3, ATH79_REG_DATA, 1));
204+
pracc_add(ctx, 0, MIPS32_LW(0, 3, ATH79_REG_DATA, 1));
205205
/* [OUTi] = $3 */
206206
pracc_add(ctx, MIPS32_PRACC_PARAM_OUT + pracc_out,
207-
MIPS32_SW(3, PRACC_OUT_OFFSET +
207+
MIPS32_SW(0, 3, PRACC_OUT_OFFSET +
208208
pracc_out, 15));
209209
pracc_out += 4;
210210
}
211211
}
212212
if (len & 3) { /* not a multiple of 4 bytes */
213213
/* $3 = [$1 + DATA] */
214-
pracc_add(ctx, 0, MIPS32_LW(3, ATH79_REG_DATA, 1));
214+
pracc_add(ctx, 0, MIPS32_LW(0, 3, ATH79_REG_DATA, 1));
215215
/* [OUTi] = $3 */
216216
pracc_add(ctx, MIPS32_PRACC_PARAM_OUT + pracc_out,
217-
MIPS32_SW(3, PRACC_OUT_OFFSET + pracc_out, 15));
217+
MIPS32_SW(0, 3, PRACC_OUT_OFFSET + pracc_out, 15));
218218
pracc_out += 4;
219219
}
220220

221221
if (ath79_info->spi.post_deselect && !partial_xfer) {
222222
const uint32_t post_deselect[] = {
223223
/* $2 = SPI_CS_DIS */
224-
MIPS32_LUI(2, UPPER16(cs_high)),
225-
MIPS32_ORI(2, 2, LOWER16(cs_high)),
224+
MIPS32_LUI(0, 2, UPPER16(cs_high)),
225+
MIPS32_ORI(0, 2, 2, LOWER16(cs_high)),
226226
/* [$1 + WRITE] = $2 */
227-
MIPS32_SW(2, ATH79_REG_WRITE, 1),
227+
MIPS32_SW(0, 2, ATH79_REG_WRITE, 1),
228228

229229
/* [$1 + FS] = 0 (disable flash io register access) */
230-
MIPS32_XORI(2, 2, 0),
231-
MIPS32_SW(2, ATH79_REG_FS, 1),
230+
MIPS32_XORI(0, 2, 2, 0),
231+
MIPS32_SW(0, 2, ATH79_REG_FS, 1),
232232
};
233233
ath79_pracc_addn(ctx, post_deselect, ARRAY_SIZE(post_deselect));
234234
}
235235

236236
/* common pracc epilogue */
237237
/* jump to start */
238-
pracc_add(ctx, 0, MIPS32_B(NEG16(ctx->code_count + 1)));
238+
pracc_add(ctx, 0, MIPS32_B(0, NEG16(ctx->code_count + 1)));
239239
/* restore $15 from DeSave */
240-
pracc_add(ctx, 0, MIPS32_MFC0(15, 31, 0));
240+
pracc_add(ctx, 0, MIPS32_MFC0(0, 15, 31, 0));
241241

242242
return pracc_out / 4;
243243
}
@@ -259,9 +259,9 @@ static int ath79_spi_bitbang_chunk(struct flash_bank *bank,
259259
const int pracc_loop_byte = 8 * 2 + 2;
260260

261261
struct pracc_queue_info ctx = {
262-
.max_code = PRACC_MAX_INSTRUCTIONS
262+
.ejtag_info = ejtag_info
263263
};
264-
int max_len = (ctx.max_code - pracc_pre_post) / pracc_loop_byte;
264+
int max_len = (PRACC_MAX_INSTRUCTIONS - pracc_pre_post) / pracc_loop_byte;
265265
int to_xfer = len > max_len ? max_len : len;
266266
int partial_xfer = len != to_xfer;
267267
int padded_len = (to_xfer + 3) & ~3;
@@ -274,22 +274,20 @@ static int ath79_spi_bitbang_chunk(struct flash_bank *bank,
274274

275275
*transferred = 0;
276276
pracc_queue_init(&ctx);
277-
if (ctx.retval != ERROR_OK)
278-
goto exit;
279277

280278
LOG_DEBUG("ath79_spi_bitbang_bytes(%p, %08x, %p, %d)",
281279
target, ath79_info->io_base, data, len);
282280

283281
LOG_DEBUG("max code %d => max len %d. to_xfer %d",
284-
ctx.max_code, max_len, to_xfer);
282+
PRACC_MAX_INSTRUCTIONS, max_len, to_xfer);
285283

286284
pracc_words = ath79_spi_bitbang_codegen(
287285
ath79_info, &ctx, data, to_xfer, partial_xfer);
288286

289287
LOG_DEBUG("Assembled %d instructions, %d stores",
290288
ctx.code_count, ctx.store_count);
291289

292-
ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, out);
290+
ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, out, 1);
293291
if (ctx.retval != ERROR_OK)
294292
goto exit;
295293

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