tcl/target/renesas_rz_g2: Rename to renesas_rz and add RZ/V2L-G3S

Rename file to get it more generic and add more targets belonging
to the same family.
Add support for two new devices: RZ/V2L and RZ/G3S

Change-Id: Idb7f4d81d2f95ad15ef686e940f43ed29f49f343
Signed-off-by: MicBiso <[email protected]>
Reviewed-on: https://review.openocd.org/c/openocd/+/8211
Reviewed-by: Antonio Borneo <[email protected]>
Tested-by: jenkins

Author: MicBiso

tcl/target/renesas_rz_g2.cfg renamed to tcl/target/renesas_rz.cfg

@@ -1,23 +1,25 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
-# Renesas RZ/G2 SOCs
+# Renesas RZ SOCs
 # - There are a combination of Cortex-A57s, Cortex-A53s, Cortex-A55, Cortex-R7
 # and Cortex-M33 for each SOC
-# - Each SOC can boot through the Cortex-A5x cores
+# - Each SOC can boot through the Cortex-A5x cores or the Cortex-M33
 
-# Supported RZ/G2 SOCs and their cores:
+# Supported RZ SOCs and their cores:
 # RZ/G2H:   Cortex-A57 x4, Cortex-A53 x4, Cortex-R7
 # RZ/G2M:   Cortex-A57 x2, Cortex-A53 x4, Cortex-R7
 # RZ/G2N:   Cortex-A57 x2,                Cortex-R7
 # RZ/G2E:                  Cortex-A53 x2, Cortex-R7
 # RZ/G2L:                  Cortex-A55 x2, Cortex-M33
+# RZ/V2L:                  Cortex-A55 x2, Cortex-M33
 # RZ/G2LC:                 Cortex-A55 x2, Cortex-M33
 # RZ/G2UL:                 Cortex-A55 x1, Cortex-M33
+# RZ/G3S:                  Cortex-A55 x1, Cortex-M33 x2
 
 # Usage:
 # There are 2 configuration options:
 # SOC:       Selects the supported SOC. (Default 'G2L')
-# BOOT_CORE: Selects the booting core. 'CA57', 'CA53' or 'CA55'
+# BOOT_CORE: Selects the booting core. 'CA57', 'CA53', 'CA55' or CM33
 
 transport select jtag
 reset_config trst_and_srst srst_gates_jtag
@@ -77,6 +79,13 @@ switch $_soc {
 		set _boot_core CA55
 		set _ap_num 0
 	}
+	V2L {
+		set _CHIPNAME r9a07g054l
+		set _num_ca55 2
+		set _num_cm33 1
+		set _boot_core CA55
+		set _ap_num 0
+	}
 	G2LC {
 		set _CHIPNAME r9a07g044c
 		set _num_ca55 2
@@ -91,6 +100,13 @@ switch $_soc {
 		set _boot_core CA55
 		set _ap_num 0
 	}
+	G3S {
+		set _CHIPNAME r9a08g045s
+		set _num_ca55 1
+		set _num_cm33 2
+		set _boot_core CA55
+		set _ap_num 0
+	}
 	default {
 		error "'$_soc' is invalid!"
 	}
@@ -112,16 +128,16 @@ if { [info exists DAP_TAPID] } {
 	set _DAP_TAPID 0x6ba00477
 }
 
-echo "\t$_soc - $_num_ca57 CA57(s), $_num_ca55 CA55(s), $_num_ca53 CA53(s), $_num_cr7 CR7(s), \
-	$_num_cm33 CM33(s)"
+echo "\t$_soc - $_num_ca57 CA57(s), $_num_ca55 CA55(s), $_num_ca53 CA53(s), \
+	$_num_cr7 CR7(s), $_num_cm33 CM33(s)"
 echo "\tBoot Core - $_boot_core\n"
 
 set _DAPNAME $_CHIPNAME.dap
 
 
 # TAP and DAP
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID \
-	-ignore-version
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
+	-expected-id $_DAP_TAPID -ignore-version
 dap create $_DAPNAME -chain-position $_CHIPNAME.cpu
 echo "$_CHIPNAME.cpu"
 
@@ -133,8 +149,8 @@ set CA53_DBGBASE {0x80C10000 0x80D10000 0x80E10000 0x80F10000}
 set CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000}
 set  CR7_DBGBASE 0x80910000
 set  CR7_CTIBASE 0x80918000
-set CM33_DBGBASE 0xE000E000
-set CM33_CTIBASE 0xE0042000
+set CM33_DBGBASE {0xE000E000 0xE010E000}
+set CM33_CTIBASE {0xE0042000 0xE0142000}
 
 set smp_targets ""
 
@@ -145,7 +161,8 @@ proc setup_a5x {core_name dbgbase ctibase num boot} {
 		cti create $_CTINAME -dap $::_DAPNAME -ap-num $::_ap_num \
 			-baseaddr [lindex $ctibase $_core]
 		target create $_TARGETNAME aarch64 -dap $::_DAPNAME \
-			-ap-num $::_ap_num -dbgbase [lindex $dbgbase $_core] -cti $_CTINAME
+			-ap-num $::_ap_num -dbgbase [lindex $dbgbase $_core] \
+			-cti $_CTINAME
 		if { $_core > 0 || $boot == 0 } {
 			$_TARGETNAME configure -defer-examine
 		}
@@ -160,13 +177,29 @@ proc setup_cr7 {dbgbase ctibase} {
 	target create $_TARGETNAME cortex_r4 -dap $::_DAPNAME \
 		-ap-num 1 -dbgbase $dbgbase -defer-examine
 }
-
-proc setup_cm33 {dbgbase ctibase} {
-        set _TARGETNAME $::_CHIPNAME.m33
-        set _CTINAME $_TARGETNAME.cti
-        cti create $_CTINAME -dap $::_DAPNAME -ap-num 2 -baseaddr $ctibase
-        target create $_TARGETNAME cortex_m -dap $::_DAPNAME \
-                -ap-num 2 -dbgbase $dbgbase -defer-examine
+proc setup_cm33 {dbgbase ctibase num boot} {
+	if { $::_soc == "G2L" || $::_soc == "V2L" \
+	|| $::_soc == "G2LC" || $::_soc == "G2UL" } {
+		set _ap_num  2
+	} elseif { $::_soc == "G3S" } {
+		set _ap_num  3
+	}
+	for { set _core 0 } { $_core < $num } { incr _core } {
+		if { $num <= 1 } {
+			set _TARGETNAME $::_CHIPNAME.m33
+		} else {
+			set _TARGETNAME $::_CHIPNAME.m33.$_core
+		}
+		set _CTINAME $_TARGETNAME.cti
+		cti create $_CTINAME -dap $::_DAPNAME -ap-num $_ap_num \
+			-baseaddr [lindex $ctibase $_core]
+		target create $_TARGETNAME cortex_m -dap $::_DAPNAME \
+			-ap-num $_ap_num -dbgbase [lindex $dbgbase $_core]
+		if { $boot == 0 } {
+			$_TARGETNAME configure -defer-examine
+		}
+		incr $_ap_num
+	}
 }
 
 # Organize target list based on the boot core
@@ -180,12 +213,17 @@ if { $_boot_core == "CA57" } {
 	setup_cr7 $CR7_DBGBASE $CR7_CTIBASE
 } elseif { $_boot_core == "CA55" } {
 	setup_a5x a55 $CA55_DBGBASE $CA55_CTIBASE $_num_ca55 1
-	setup_cm33 $CM33_DBGBASE $CM33_CTIBASE
+	setup_cm33 $CM33_DBGBASE $CM33_CTIBASE $_num_cm33 0
+} elseif { $_boot_core == "CM33" } {
+	setup_a5x a55 $CA55_DBGBASE $CA55_CTIBASE $_num_ca55 0
+	setup_cm33 $CM33_DBGBASE $CM33_CTIBASE $_num_cm33 1
 }
+
 echo "SMP targets:$smp_targets"
 eval "target smp $smp_targets"
 
-if { $_soc == "G2L" || $_soc == "G2LC" || $_soc == "G2UL" } {
+if { $_soc == "G2L" || $_soc == "V2L" || $_soc == "G2LC" \
+|| $_soc == "G2UL" || $_soc == "G3S"} {
 	target create $_CHIPNAME.axi_ap mem_ap -dap $_DAPNAME -ap-num 1
 }