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timsifivetimsifive
authored
Merge pull request #67 from riscv/cosmetics
Various cosmetic improvements
2 parents 91c3dcc + 4d264b3 commit 8d79a7c

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3 files changed

+147
-77
lines changed

3 files changed

+147
-77
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‎src/target/riscv/debug_defines.h‎

Lines changed: 58 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -84,7 +84,7 @@
8484
/*
8585
* 0: Version described in spec version 0.11.
8686
*
87-
* 1: Version described in spec version 0.12 (and later?), which
87+
* 1: Version described in spec version 0.13 (and later?), which
8888
* reduces the DMI data width to 32 bits.
8989
*
9090
* Other values are reserved for future use.
@@ -110,7 +110,12 @@
110110
/*
111111
* When the debugger writes this field, it has the following meaning:
112112
*
113-
* 0: Ignore \Fdata. (nop)
113+
* 0: Ignore \Fdata and \Faddress. (nop)
114+
*
115+
* Don't send anything over the DMI during Update-DR.
116+
* This operation should never result in a busy or error response.
117+
* The address and data reported in the following Capture-DR
118+
* are undefined.
114119
*
115120
* 1: Read from \Faddress. (read)
116121
*
@@ -151,13 +156,11 @@
151156
/*
152157
* 0: There is no external debug support.
153158
*
154-
* 1: External debug support exists as it is described in this document.
155-
*
156-
* Other values are reserved for future standards.
159+
* 4: External debug support exists as it is described in this document.
157160
*/
158-
#define CSR_DCSR_XDEBUGVER_OFFSET 30
159-
#define CSR_DCSR_XDEBUGVER_LENGTH 2
160-
#define CSR_DCSR_XDEBUGVER (0x3 << CSR_DCSR_XDEBUGVER_OFFSET)
161+
#define CSR_DCSR_XDEBUGVER_OFFSET 28
162+
#define CSR_DCSR_XDEBUGVER_LENGTH 4
163+
#define CSR_DCSR_XDEBUGVER (0xf << CSR_DCSR_XDEBUGVER_OFFSET)
161164
/*
162165
* When 1, {\tt ebreak} instructions in Machine Mode enter Debug Mode.
163166
*/
@@ -230,8 +233,11 @@
230233
#define CSR_DCSR_CAUSE (0x7 << CSR_DCSR_CAUSE_OFFSET)
231234
/*
232235
* When set and not in Debug Mode, the hart will only execute a single
233-
* instruction, and then enter Debug Mode. Interrupts are disabled
234-
* when this bit is set.
236+
* instruction and then enter Debug Mode.
237+
* Interrupts are disabled when this bit is set.
238+
* If the instruction does not complete due to an exception,
239+
* the hart will immediately enter Debug Mode before executing
240+
* the trap handler, with appropriate exception registers set.
235241
*/
236242
#define CSR_DCSR_STEP_OFFSET 2
237243
#define CSR_DCSR_STEP_LENGTH 1
@@ -255,16 +261,6 @@
255261
#define CSR_DPC_DPC (((1L<<XLEN)-1) << CSR_DPC_DPC_OFFSET)
256262
#define CSR_DSCRATCH0 0x7b2
257263
#define CSR_DSCRATCH1 0x7b3
258-
#define CSR_PRIV virtual
259-
/*
260-
* Contains the privilege level the hart was operating in when Debug
261-
* Mode was entered. The encoding is described in Table
262-
* \ref{tab:privlevel}. A user can write this value to change the
263-
* hart's privilege level when exiting Debug Mode.
264-
*/
265-
#define CSR_PRIV_PRV_OFFSET 0
266-
#define CSR_PRIV_PRV_LENGTH 2
267-
#define CSR_PRIV_PRV (0x3 << CSR_PRIV_PRV_OFFSET)
268264
#define CSR_TSELECT 0x7a0
269265
#define CSR_TSELECT_INDEX_OFFSET 0
270266
#define CSR_TSELECT_INDEX_LENGTH XLEN
@@ -485,28 +481,28 @@
485481
#define CSR_ICOUNT_COUNT_LENGTH 14
486482
#define CSR_ICOUNT_COUNT (0x3fffL << CSR_ICOUNT_COUNT_OFFSET)
487483
/*
488-
* When set, every instruction completed in M mode decrements \Fcount
484+
* When set, every instruction completed or exception taken in M mode decrements \Fcount
489485
* by 1.
490486
*/
491487
#define CSR_ICOUNT_M_OFFSET 9
492488
#define CSR_ICOUNT_M_LENGTH 1
493489
#define CSR_ICOUNT_M (0x1L << CSR_ICOUNT_M_OFFSET)
494490
/*
495-
* When set, every instruction completed in H mode decrements \Fcount
491+
* When set, every instruction completed or exception taken in in H mode decrements \Fcount
496492
* by 1.
497493
*/
498494
#define CSR_ICOUNT_H_OFFSET 8
499495
#define CSR_ICOUNT_H_LENGTH 1
500496
#define CSR_ICOUNT_H (0x1L << CSR_ICOUNT_H_OFFSET)
501497
/*
502-
* When set, every instruction completed in S mode decrements \Fcount
498+
* When set, every instruction completed or exception taken in S mode decrements \Fcount
503499
* by 1.
504500
*/
505501
#define CSR_ICOUNT_S_OFFSET 7
506502
#define CSR_ICOUNT_S_LENGTH 1
507503
#define CSR_ICOUNT_S (0x1L << CSR_ICOUNT_S_OFFSET)
508504
/*
509-
* When set, every instruction completed in U mode decrements \Fcount
505+
* When set, every instruction completed or exception taken in U mode decrements \Fcount
510506
* by 1.
511507
*/
512508
#define CSR_ICOUNT_U_OFFSET 6
@@ -619,29 +615,24 @@
619615
#define DMI_DMSTATUS_CFGSTRVALID_LENGTH 1
620616
#define DMI_DMSTATUS_CFGSTRVALID (0x1 << DMI_DMSTATUS_CFGSTRVALID_OFFSET)
621617
/*
622-
* Reserved for future use. Reads as 0.
623-
*/
624-
#define DMI_DMSTATUS_VERSIONHI_OFFSET 2
625-
#define DMI_DMSTATUS_VERSIONHI_LENGTH 2
626-
#define DMI_DMSTATUS_VERSIONHI (0x3 << DMI_DMSTATUS_VERSIONHI_OFFSET)
627-
/*
628-
* 00: There is no Debug Module present.
618+
* 0: There is no Debug Module present.
629619
*
630-
* 01: There is a Debug Module and it conforms to version 0.11 of this
620+
* 1: There is a Debug Module and it conforms to version 0.11 of this
631621
* specification.
632622
*
633-
* 10: There is a Debug Module and it conforms to version 0.13 of this
623+
* 2: There is a Debug Module and it conforms to version 0.13 of this
634624
* specification.
635-
*
636-
* 11: Reserved for future use.
637625
*/
638-
#define DMI_DMSTATUS_VERSIONLO_OFFSET 0
639-
#define DMI_DMSTATUS_VERSIONLO_LENGTH 2
640-
#define DMI_DMSTATUS_VERSIONLO (0x3 << DMI_DMSTATUS_VERSIONLO_OFFSET)
626+
#define DMI_DMSTATUS_VERSION_OFFSET 0
627+
#define DMI_DMSTATUS_VERSION_LENGTH 4
628+
#define DMI_DMSTATUS_VERSION (0xf << DMI_DMSTATUS_VERSION_OFFSET)
641629
#define DMI_DMCONTROL 0x10
642630
/*
643-
* Halt request signal for all currently selected harts. When set to 1, the
644-
* hart will halt if it is not currently halted.
631+
* Halt request signal for all currently selected harts. When set to
632+
* 1, each selected hart will halt if it is not currently halted.
633+
*
634+
* Writing 1 or 0 has no effect on a hart which is already halted, but
635+
* the bit should be cleared to 0 before the hart is resumed.
645636
* Setting both \Fhaltreq and \Fresumereq leads to undefined behavior.
646637
*
647638
* Writes apply to the new value of \Fhartsel and \Fhasel.
@@ -651,7 +642,7 @@
651642
#define DMI_DMCONTROL_HALTREQ (0x1 << DMI_DMCONTROL_HALTREQ_OFFSET)
652643
/*
653644
* Resume request signal for all currently selected harts. When set to 1,
654-
* the hart will resume if it is currently halted.
645+
* each selected hart will resume if it is currently halted.
655646
* Setting both \Fhaltreq and \Fresumereq leads to undefined behavior.
656647
*
657648
* Writes apply to the new value of \Fhartsel and \Fhasel.
@@ -698,8 +689,11 @@
698689
#define DMI_DMCONTROL_HARTSEL (0x3ff << DMI_DMCONTROL_HARTSEL_OFFSET)
699690
/*
700691
* This bit controls the reset signal from the DM to the rest of the
701-
* system. To perform a reset the debugger writes 1, and then writes 0
702-
* to deassert the reset.
692+
* system. To perform a system reset the debugger writes 1,
693+
* and then writes 0
694+
* to deassert the reset. This bit must not reset the Debug Module
695+
* registers. What it does reset is platform-specific (it may
696+
* reset nothing).
703697
*/
704698
#define DMI_DMCONTROL_NDMRESET_OFFSET 1
705699
#define DMI_DMCONTROL_NDMRESET_LENGTH 1
@@ -717,8 +711,8 @@
717711
* Debug Module after power up, including the platform's system reset
718712
* or Debug Transport reset signals.
719713
*
720-
* A debugger should pulse this bit low to ensure that the Debug
721-
* Module is fully reset and ready to use.
714+
* A debugger may pulse this bit low to get the debug module into a
715+
* known state.
722716
*
723717
* Implementations may use this bit to aid debugging, for example by
724718
* preventing the Debug Module from being power gated while debugging
@@ -899,8 +893,9 @@
899893
*
900894
* 0 (none): No error.
901895
*
902-
* 1 (busy): An abstract command was executing while \Rcommand or one
903-
* of the {\tt data} registers was accessed.
896+
* 1 (busy): An abstract command was executing while \Rcommand,
897+
* \Rabstractcs, \Rabstractauto was written, or when one
898+
* of the {\tt data} or {\tt progbuf} registers was read or written.
904899
*
905900
* 2 (not supported): The requested command is not supported. A
906901
* command that is not supported while the hart is running may be
@@ -919,7 +914,7 @@
919914
#define DMI_ABSTRACTCS_CMDERR (0x7 << DMI_ABSTRACTCS_CMDERR_OFFSET)
920915
/*
921916
* Number of {\tt data} registers that are implemented as part of the
922-
* abstract command interface. Valid sizes are 0 - 8.
917+
* abstract command interface. Valid sizes are 0 - 12.
923918
*/
924919
#define DMI_ABSTRACTCS_DATACOUNT_OFFSET 0
925920
#define DMI_ABSTRACTCS_DATACOUNT_LENGTH 5
@@ -1138,7 +1133,7 @@
11381133
*
11391134
* 3: There was some other error (eg. alignment).
11401135
*
1141-
* 4: The system bus master was busy when a one of the
1136+
* 4: The system bus master was busy when one of the
11421137
* {\tt sbaddress} or {\tt sbdata} registers was written,
11431138
* or the {\tt sbdata} register was read when it had
11441139
* stale data.
@@ -1396,7 +1391,10 @@
13961391
#define AC_ACCESS_REGISTER_WRITE_LENGTH 1
13971392
#define AC_ACCESS_REGISTER_WRITE (0x1 << AC_ACCESS_REGISTER_WRITE_OFFSET)
13981393
/*
1399-
* Number of the register to access, as described in Table~\ref{tab:regno}.
1394+
* Number of the register to access, as described in
1395+
* Table~\ref{tab:regno}.
1396+
* \Rdpc may be used as an alias for PC if this command is
1397+
* supported on a non-halted hart.
14001398
*/
14011399
#define AC_ACCESS_REGISTER_REGNO_OFFSET 0
14021400
#define AC_ACCESS_REGISTER_REGNO_LENGTH 16
@@ -1408,3 +1406,13 @@
14081406
#define AC_QUICK_ACCESS_CMDTYPE_OFFSET 24
14091407
#define AC_QUICK_ACCESS_CMDTYPE_LENGTH 8
14101408
#define AC_QUICK_ACCESS_CMDTYPE (0xff << AC_QUICK_ACCESS_CMDTYPE_OFFSET)
1409+
#define VIRT_PRIV virtual
1410+
/*
1411+
* Contains the privilege level the hart was operating in when Debug
1412+
* Mode was entered. The encoding is described in Table
1413+
* \ref{tab:privlevel}. A user can write this value to change the
1414+
* hart's privilege level when exiting Debug Mode.
1415+
*/
1416+
#define VIRT_PRIV_PRV_OFFSET 0
1417+
#define VIRT_PRIV_PRV_LENGTH 2
1418+
#define VIRT_PRIV_PRV (0x3 << VIRT_PRIV_PRV_OFFSET)

‎src/target/riscv/program.c‎

Lines changed: 14 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -17,8 +17,6 @@ int riscv_program_lal(struct riscv_program *p, enum gdb_regno d, riscv_addr_t ad
1717
/* Program interface. */
1818
int riscv_program_init(struct riscv_program *p, struct target *target)
1919
{
20-
LOG_DEBUG("riscv_program_init: p=%p", p);
21-
2220
memset(p, 0, sizeof(*p));
2321
p->target = target;
2422
p->instruction_count = 0;
@@ -72,14 +70,19 @@ int riscv_program_exec(struct riscv_program *p, struct target *t)
7270
return ERROR_FAIL;
7371
}
7472

75-
for (size_t i = 0; i < riscv_debug_buffer_size(p->target); ++i) {
76-
LOG_DEBUG("Executing program %p: debug_buffer[%02x] = DASM(0x%08lx)", p, (int)i, (long)p->debug_buffer[i]);
77-
if (i <= p->instruction_count || i >= riscv_debug_buffer_size(p->target) - p->data_count)
73+
for (unsigned i = 0; i < riscv_debug_buffer_size(p->target); ++i) {
74+
if (i < p->instruction_count) {
75+
LOG_DEBUG("%p: debug_buffer[%02x] = DASM(0x%08x)", p, i, p->debug_buffer[i]);
76+
riscv_write_debug_buffer(t, i, p->debug_buffer[i]);
77+
}
78+
if (i >= riscv_debug_buffer_size(p->target) - p->data_count) {
79+
LOG_DEBUG("%p: debug_buffer[%02x] = 0x%08x", p, i, p->debug_buffer[i]);
7880
riscv_write_debug_buffer(t, i, p->debug_buffer[i]);
81+
}
7982
}
8083

8184
if (riscv_execute_debug_buffer(t) != ERROR_OK) {
82-
LOG_DEBUG("Unable to execute program %p", p);
85+
LOG_ERROR("Unable to execute program %p", p);
8386
return ERROR_FAIL;
8487
}
8588

@@ -96,8 +99,6 @@ int riscv_program_exec(struct riscv_program *p, struct target *t)
9699

97100
riscv_addr_t riscv_program_alloc_data(struct riscv_program *p, size_t bytes)
98101
{
99-
LOG_DEBUG("allocating %d bytes of data", (int)bytes);
100-
101102
riscv_addr_t addr =
102103
riscv_debug_buffer_addr(p->target)
103104
+ riscv_debug_buffer_size(p->target) * sizeof(p->debug_buffer[0])
@@ -110,11 +111,10 @@ riscv_addr_t riscv_program_alloc_data(struct riscv_program *p, size_t bytes)
110111
+ p->instruction_count * sizeof(p->debug_buffer[0]);
111112

112113
if (addr <= ptop) {
113-
LOG_DEBUG("unable to allocate %d bytes", (int)bytes);
114+
LOG_ERROR("unable to allocate %d bytes", (int)bytes);
114115
return RISCV_PROGRAM_ALLOC_FAIL;
115116
}
116117

117-
LOG_DEBUG("allocated %d bytes at 0x%08lx", (int)bytes, (long)addr);
118118
p->data_count =
119119
+ riscv_debug_buffer_size(p->target)
120120
- (addr - riscv_debug_buffer_addr(p->target)) / sizeof(p->debug_buffer[0]);
@@ -474,17 +474,14 @@ int riscv_program_lal(struct riscv_program *p, enum gdb_regno d, riscv_addr_t ad
474474

475475
int riscv_program_insert(struct riscv_program *p, riscv_insn_t i)
476476
{
477-
LOG_DEBUG("instruction_count: %d (p=%p)", (int)p->instruction_count, p);
478-
479477
if (p->instruction_count + p->data_count + 1 > riscv_debug_buffer_size(p->target)) {
480-
LOG_DEBUG("Unable to insert instruction:");
481-
LOG_DEBUG(" instruction_count=%d", (int)p->instruction_count);
482-
LOG_DEBUG(" data_count =%d", (int)p->data_count);
483-
LOG_DEBUG(" buffer size =%d", (int)riscv_debug_buffer_size(p->target));
478+
LOG_ERROR("Unable to insert instruction:");
479+
LOG_ERROR(" instruction_count=%d", (int)p->instruction_count);
480+
LOG_ERROR(" data_count =%d", (int)p->data_count);
481+
LOG_ERROR(" buffer size =%d", (int)riscv_debug_buffer_size(p->target));
484482
return ERROR_FAIL;
485483
}
486484

487-
LOG_DEBUG("PROGBUF[%d] = DASM(0x%08x) [0x%08x]", (int)p->instruction_count, i, i);
488485
p->debug_buffer[p->instruction_count] = i;
489486
p->instruction_count++;
490487
return ERROR_OK;

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