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timsifivetimsifive
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Clean up fespi flashing code (#313)
* WIP upstream review feedback. See http://openocd.zylin.com/#/c/4656/ The main change is to get rid of macros that contain a return statement. Change-Id: Iff79a8aa7c40ee04a8d1f07d973f9b29d4899d5c * Remove unaligned head/tail code. From inspection it's not clear to me that this is necessary at all. I've been unable to make a test case that results in anything besides a 4-byte aligned flash to happen. Sections that aren't multiples of 4 are common, and appear to work fine. Change-Id: Idb6109ca015ae06b9d8f16bd883f9c8f5c51087d * Move fespi native code into contrib/loaders As suggested by http://openocd.zylin.com/#/c/4656/ Change-Id: I275012aa8a1ef6a0e8a2ec8ebe8643d87de24407 * Reenable hw mode if errors happen without it. Change-Id: I1220033c13d02e8a441992bd6daa0ec3b5acbfca * Default flash to not protected. Requested by upstream review. Change-Id: I61753bd9909d7f21ef6624037a865072c18bd1d8
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4 files changed

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‎contrib/loaders/flash/fespi/Makefile‎

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BIN2C = ../../../../src/helper/bin2char.sh
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CROSS_COMPILE ?= riscv64-unknown-elf-
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CC=$(CROSS_COMPILE)gcc
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OBJCOPY=$(CROSS_COMPILE)objcopy
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OBJDUMP=$(CROSS_COMPILE)objdump
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CFLAGS = -march=rv32i -mabi=ilp32 -x assembler-with-cpp - -nostdlib -nostartfiles
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all: fespi.inc
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.PHONY: clean
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%.elf: %.S
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$(CC) $(CFLAGS) $< -o $@
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%.lst: %.elf
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$(OBJDUMP) -S $< > $@
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%.bin: %.elf
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$(OBJCOPY) -Obinary $< $@
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%.inc: %.bin
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$(BIN2C) < $< > $@
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clean:
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-rm -f *.elf *.lst *.bin *.inc

‎contrib/loaders/flash/fespi/fespi.S‎

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#define SPIFLASH_READ_STATUS 0x05 // Read Status Register
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#define SPIFLASH_BSY_BIT 0x00000001 // WIP Bit of SPI SR on SMI SR
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// Register offsets
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#define FESPI_REG_FMT 0x40
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#define FESPI_REG_TXFIFO 0x48
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#define FESPI_REG_RXFIFO 0x4c
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#define FESPI_REG_IP 0x74
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// Fields
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#define FESPI_IP_TXWM 0x1
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#define FESPI_FMT_DIR(x) (((x) & 0x1) << 3)
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// To enter, jump to the start of command_table (ie. offset 0).
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// a0 - FESPI base address
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// a1 - start address of buffer
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// The buffer contains a "program" in byte sequences. The first byte in a
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// sequence determines the operation. Some operation will read more data from
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// the program, while some will not. The operation byte is the offset into
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// command_table, so eg. 4 means exit, 8 means transmit, and so on.
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.global _start
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_start:
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command_table:
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j main // 0
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ebreak // 4
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j tx // 8
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j txwm_wait // 12
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j write_reg // 16
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j wip_wait // 20
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j set_dir // 24
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// Execute the program.
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main:
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lbu t0, 0(a1)
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addi a1, a1, 1
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la t1, command_table
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add t0, t0, t1
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jr t0
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// Read 1 byte the contains the number of bytes to transmit. Then read those
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// bytes from the program and transmit them one by one.
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tx:
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lbu t1, 0(a1) // read number of bytes to transmit
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addi a1, a1, 1
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1: lw t0, FESPI_REG_TXFIFO(a0) // wait for FIFO clear
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bltz t0, 1b
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lbu t0, 0(a1) // Load byte to write
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sw t0, FESPI_REG_TXFIFO(a0)
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addi a1, a1, 1
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addi t1, t1, -1
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bgtz t1, 1b
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j main
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// Wait until TXWM is set.
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txwm_wait:
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1: lw t0, FESPI_REG_IP(a0)
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andi t0, t0, FESPI_IP_TXWM
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beqz t0, 1b
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j main
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// Read 1 byte that contains the offset of the register to write, and 1 byte
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// that contains the data to write.
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write_reg:
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lbu t0, 0(a1) // read register to write
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add t0, t0, a0
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lbu t1, 1(a1) // read value to write
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addi a1, a1, 2
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sw t1, 0(t0)
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j main
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wip_wait:
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li a2, SPIFLASH_READ_STATUS
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jal txrx_byte
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// discard first result
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1: li a2, 0
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jal txrx_byte
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andi t0, a2, SPIFLASH_BSY_BIT
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bnez t0, 1b
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j main
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txrx_byte: // transmit the byte in a2, receive a bit into a2
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lw t0, FESPI_REG_TXFIFO(a0) // wait for FIFO clear
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bltz t0, txrx_byte
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sw a2, FESPI_REG_TXFIFO(a0)
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1: lw a2, FESPI_REG_RXFIFO(a0)
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bltz a2, 1b
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ret
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set_dir:
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lw t0, FESPI_REG_FMT(a0)
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li t1, ~(FESPI_FMT_DIR(0xFFFFFFFF))
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and t0, t0, t1
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lbu t1, 0(a1) // read value to OR in
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addi a1, a1, 1
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or t0, t0, t1
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sw t0, FESPI_REG_FMT(a0)
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j main

‎contrib/loaders/flash/fespi/fespi.inc‎

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/* Autogenerated with ../../../../src/helper/bin2char.sh */
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0x6f,0x00,0xc0,0x01,0x73,0x00,0x10,0x00,0x6f,0x00,0xc0,0x02,0x6f,0x00,0x00,0x05,
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0xb3,0x82,0xa2,0x00,0x03,0xc3,0x15,0x00,0x93,0x85,0x25,0x00,0x23,0xa0,0x62,0x00,
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0x6f,0xf0,0xdf,0xf9,0x13,0x06,0x50,0x00,0xef,0x00,0x80,0x01,0x13,0x06,0x00,0x00,
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0xef,0x00,0x00,0x01,0x93,0x72,0x16,0x00,0xe3,0x9a,0x02,0xfe,0x6f,0xf0,0x1f,0xf8,
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0x83,0x22,0x85,0x04,0xe3,0xce,0x02,0xfe,0x23,0x24,0xc5,0x04,0x03,0x26,0xc5,0x04,
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0xe3,0x4e,0x06,0xfe,0x67,0x80,0x00,0x00,0x83,0x22,0x05,0x04,0x13,0x03,0x70,0xff,
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0xb3,0xf2,0x62,0x00,0x03,0xc3,0x05,0x00,0x93,0x85,0x15,0x00,0xb3,0xe2,0x62,0x00,
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0x23,0x20,0x55,0x04,0x6f,0xf0,0x9f,0xf4,

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