@@ -2902,6 +2902,15 @@ static int deassert_reset(struct target *target)
29022902 riscv_scan_set_delay (& info -> learned_delays , RISCV_DELAY_BASE ,
29032903 orig_base_delay );
29042904
2905+ /* Ack reset and clear DM_DMCONTROL_HALTREQ if previously set */
2906+ control = 0 ;
2907+ control = set_field (control , DM_DMCONTROL_DMACTIVE , 1 );
2908+ control = set_field (control , DM_DMCONTROL_ACKHAVERESET , 1 );
2909+ control = set_dmcontrol_hartsel (control , info -> index );
2910+ result = dm_write (target , DM_DMCONTROL , control );
2911+ if (result != ERROR_OK )
2912+ return result ;
2913+
29052914 if (target -> reset_halt ) {
29062915 target -> state = TARGET_HALTED ;
29072916 target -> debug_reason = DBG_REASON_DBGRQ ;
@@ -2910,13 +2919,7 @@ static int deassert_reset(struct target *target)
29102919 target -> debug_reason = DBG_REASON_NOTHALTED ;
29112920 }
29122921 info -> dcsr_ebreak_is_set = dcsr_ebreak_config_equals_reset_value (target );
2913-
2914- /* Ack reset and clear DM_DMCONTROL_HALTREQ if previously set */
2915- control = 0 ;
2916- control = set_field (control , DM_DMCONTROL_DMACTIVE , 1 );
2917- control = set_field (control , DM_DMCONTROL_ACKHAVERESET , 1 );
2918- control = set_dmcontrol_hartsel (control , info -> index );
2919- return dm_write (target , DM_DMCONTROL , control );
2922+ return ERROR_OK ;
29202923}
29212924
29222925static int execute_fence (struct target * target )
0 commit comments