target/riscv: extend trigger controls

* Add control for action mode.
* Introduce `riscv mtrigger` command.

Author: lz-bro

doc/openocd.texi

@@ -11728,12 +11728,15 @@ set those triggers directly. (It's also possible to do so by writing the
 appropriate CSRs.)
 
 @deffn {Command} {riscv etrigger set} [@option{m}] [@option{s}] [@option{u}] [@option{vs}] [@option{vu}] exception_codes
-Set an exception trigger (type 5) on the current target, which halts the target when it
-fires.  @option{m}, @option{s}, @option{u}, @option{vs}, and @option{vu} control
-which execution modes the trigger fires in. @var{exception_codes} is a bit
-field, where each bit corresponds to an exception code in mcause (defined in the
-RISC-V Privileged Spec). The etrigger will fire on the exceptions whose bits are
-set in @var{exception_codes}.
+[@option{exception}|@option{halt}|@option{trace_on}|@option{trace_off}|@option{trace_notify}]
+Set an exception trigger (type 5) on the current target, which sets the desired behavior on
+the target when it fires.  @option{m}, @option{s}, @option{u}, @option{vs}, and @option{vu}
+control which execution modes the trigger fires in. @var{exception_codes} is a bit field,
+where each bit corresponds to an exception code in mcause (defined in the RISC-V Privileged Spec).
+The etrigger will fire on the exceptions whose bits are set in @var{exception_codes}.
+@option{exception}|@option{halt}|@option{trace_on}|@option{trace_off}|@option{trace_notify}
+control the desired behavior on the target when the trigger fires. Defaults to @option{halt},
+which halts the target.
 
 For details on this trigger type, see the RISC-V Debug Specification.
 @end deffn
@@ -11743,14 +11746,16 @@ Clear the type 5 trigger that was set using @command{riscv etrigger set}.
 @end deffn
 
 @deffn {Command} {riscv icount set} [@option{m}] [@option{s}] [@option{u}] [@option{vs}] [@option{vu}] [@option{pending}] count
-Set an instruction count
-trigger (type 3) on the current target, which halts the target when it fires.
-@option{m}, @option{s}, @option{u}, @option{vs}, and @option{vu} control which
-execution modes the trigger fires in. If [@option{pending}] is passed then the
-pending bit is set, which is unlikely to be useful unless you're debugging the
-hardware implementation of this trigger.
-@var{count} sets the number of instructions to execute before the trigger is
-taken.
+[@option{exception}|@option{halt}|@option{trace_on}|@option{trace_off}|@option{trace_notify}]
+Set an instruction count trigger (type 3) on the current target, which sets the desired behavior
+on the target when it fires. @option{m}, @option{s}, @option{u}, @option{vs}, and @option{vu}
+control which execution modes the trigger fires in. If [@option{pending}] is passed then the
+pending bit is set, which is unlikely to be useful unless you're debugging the hardware
+implementation of this trigger. @var{count} sets the number of instructions to execute before
+the trigger is taken.
+@option{exception}|@option{halt}|@option{trace_on}|@option{trace_off}|@option{trace_notify}
+control the desired behavior on the target when the trigger fires. Defaults to @option{halt},
+which halts the target.
 
 For details on this trigger type, see the RISC-V Debug Specification.
 @end deffn
@@ -11760,12 +11765,16 @@ Clear the type 3 trigger that was set using @command{riscv icount set}.
 @end deffn
 
 @deffn {Command} {riscv itrigger set} [@option{m}] [@option{s}] [@option{u}] [@option{vs}] [@option{vu}] [@option{nmi}] mie_bits
-Set an interrupt trigger (type 4) on the current target, which halts the target when it
-fires.  @option{m}, @option{s}, @option{u}, @option{vs}, and @option{vu} control
-which execution modes the trigger fires in.  If [@option{nmi}] is passed then
-the trigger will fire on non-maskable interrupts in those modes. @var{mie_bits}
-controls which interrupts the trigger fires on, using the same bit assignments
-as in the mie CSR (defined in the RISC-V Privileged Spec).
+[@option{exception}|@option{halt}|@option{trace_on}|@option{trace_off}|@option{trace_notify}]
+Set an interrupt trigger (type 4) on the current target, which sets the desired behavior on
+the target when it fires.  @option{m}, @option{s}, @option{u}, @option{vs}, and @option{vu}
+control which execution modes the trigger fires in.  If [@option{nmi}] is passed then the
+trigger will fire on non-maskable interrupts in those modes. @var{mie_bits} controls which
+interrupts the trigger fires on, using the same bit assignments as in the mie CSR (defined
+in the RISC-V Privileged Spec).
+@option{exception}|@option{halt}|@option{trace_on}|@option{trace_off}|@option{trace_notify}
+control the desired behavior on the target when the trigger fires. Defaults to @option{halt},
+which halts the target.
 
 For details on this trigger type, see the RISC-V Debug Specification.
 @end deffn