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Fix indentation to match OpenOCD style.
This change is just in the whitespace. There are no code changes. See http://openocd.org/doc-release/doxygen/stylec.html
1 parent 363a0a2 commit ac2da40

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6 files changed

+333
-335
lines changed

6 files changed

+333
-335
lines changed

‎src/target/riscv/asm.h‎

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -6,31 +6,31 @@
66
/*** Version-independent functions that we don't want in the main address space. ***/
77

88
static uint32_t load(const struct target *target, unsigned int rd,
9-
unsigned int base, uint16_t offset) __attribute__ ((unused));
9+
unsigned int base, uint16_t offset) __attribute__ ((unused));
1010
static uint32_t load(const struct target *target, unsigned int rd,
11-
unsigned int base, uint16_t offset)
11+
unsigned int base, uint16_t offset)
1212
{
13-
switch (riscv_xlen(target)) {
14-
case 32:
15-
return lw(rd, base, offset);
16-
case 64:
17-
return ld(rd, base, offset);
18-
}
19-
assert(0);
13+
switch (riscv_xlen(target)) {
14+
case 32:
15+
return lw(rd, base, offset);
16+
case 64:
17+
return ld(rd, base, offset);
18+
}
19+
assert(0);
2020
}
2121

2222
static uint32_t store(const struct target *target, unsigned int src,
23-
unsigned int base, uint16_t offset) __attribute__ ((unused));
23+
unsigned int base, uint16_t offset) __attribute__ ((unused));
2424
static uint32_t store(const struct target *target, unsigned int src,
25-
unsigned int base, uint16_t offset)
25+
unsigned int base, uint16_t offset)
2626
{
27-
switch (riscv_xlen(target)) {
28-
case 32:
29-
return sw(src, base, offset);
30-
case 64:
31-
return sd(src, base, offset);
32-
}
33-
assert(0);
27+
switch (riscv_xlen(target)) {
28+
case 32:
29+
return sw(src, base, offset);
30+
case 64:
31+
return sd(src, base, offset);
32+
}
33+
assert(0);
3434
}
3535

3636
#endif

‎src/target/riscv/batch.c‎

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -123,34 +123,34 @@ void riscv_batch_add_nop(struct riscv_batch *batch)
123123

124124
void dump_field(const struct scan_field *field)
125125
{
126-
static const char *op_string[] = {"-", "r", "w", "?"};
127-
static const char *status_string[] = {"+", "?", "F", "b"};
126+
static const char *op_string[] = {"-", "r", "w", "?"};
127+
static const char *status_string[] = {"+", "?", "F", "b"};
128128

129-
if (debug_level < LOG_LVL_DEBUG)
130-
return;
129+
if (debug_level < LOG_LVL_DEBUG)
130+
return;
131131

132132
assert(field->out_value != NULL);
133-
uint64_t out = buf_get_u64(field->out_value, 0, field->num_bits);
134-
unsigned int out_op = get_field(out, DTM_DMI_OP);
135-
unsigned int out_data = get_field(out, DTM_DMI_DATA);
136-
unsigned int out_address = out >> DTM_DMI_ADDRESS_OFFSET;
137-
138-
if (field->in_value) {
139-
uint64_t in = buf_get_u64(field->in_value, 0, field->num_bits);
140-
unsigned int in_op = get_field(in, DTM_DMI_OP);
141-
unsigned int in_data = get_field(in, DTM_DMI_DATA);
142-
unsigned int in_address = in >> DTM_DMI_ADDRESS_OFFSET;
143-
144-
log_printf_lf(LOG_LVL_DEBUG,
145-
__FILE__, __LINE__, __PRETTY_FUNCTION__,
146-
"%db %s %08x @%02x -> %s %08x @%02x [0x%p -> 0x%p]",
147-
field->num_bits,
148-
op_string[out_op], out_data, out_address,
149-
status_string[in_op], in_data, in_address,
133+
uint64_t out = buf_get_u64(field->out_value, 0, field->num_bits);
134+
unsigned int out_op = get_field(out, DTM_DMI_OP);
135+
unsigned int out_data = get_field(out, DTM_DMI_DATA);
136+
unsigned int out_address = out >> DTM_DMI_ADDRESS_OFFSET;
137+
138+
if (field->in_value) {
139+
uint64_t in = buf_get_u64(field->in_value, 0, field->num_bits);
140+
unsigned int in_op = get_field(in, DTM_DMI_OP);
141+
unsigned int in_data = get_field(in, DTM_DMI_DATA);
142+
unsigned int in_address = in >> DTM_DMI_ADDRESS_OFFSET;
143+
144+
log_printf_lf(LOG_LVL_DEBUG,
145+
__FILE__, __LINE__, __PRETTY_FUNCTION__,
146+
"%db %s %08x @%02x -> %s %08x @%02x [0x%p -> 0x%p]",
147+
field->num_bits,
148+
op_string[out_op], out_data, out_address,
149+
status_string[in_op], in_data, in_address,
150150
field->out_value, field->in_value);
151-
} else {
152-
log_printf_lf(LOG_LVL_DEBUG,
153-
__FILE__, __LINE__, __PRETTY_FUNCTION__, "%db %s %08x @%02x -> ?",
154-
field->num_bits, op_string[out_op], out_data, out_address);
155-
}
151+
} else {
152+
log_printf_lf(LOG_LVL_DEBUG,
153+
__FILE__, __LINE__, __PRETTY_FUNCTION__, "%db %s %08x @%02x -> ?",
154+
field->num_bits, op_string[out_op], out_data, out_address);
155+
}
156156
}

‎src/target/riscv/gdb_regs.h‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -2,27 +2,27 @@
22
#define TARGET__RISCV__GDB_REGS_H
33

44
enum gdb_regno {
5-
GDB_REGNO_XPR0 = 0,
5+
GDB_REGNO_XPR0 = 0,
66
GDB_REGNO_X0 = GDB_REGNO_XPR0 + 0,
77
GDB_REGNO_ZERO = GDB_REGNO_XPR0 + 0,
88
GDB_REGNO_S0 = GDB_REGNO_XPR0 + 8,
99
GDB_REGNO_S1 = GDB_REGNO_XPR0 + 9,
10-
GDB_REGNO_XPR31 = GDB_REGNO_XPR0 + 31,
11-
GDB_REGNO_PC = 32,
12-
GDB_REGNO_FPR0 = 33,
13-
GDB_REGNO_FPR31 = GDB_REGNO_FPR0 + 31,
14-
GDB_REGNO_CSR0 = 65,
15-
GDB_REGNO_TSELECT = CSR_TSELECT + GDB_REGNO_CSR0,
16-
GDB_REGNO_TDATA1 = CSR_TDATA1 + GDB_REGNO_CSR0,
17-
GDB_REGNO_TDATA2 = CSR_TDATA2 + GDB_REGNO_CSR0,
18-
GDB_REGNO_MISA = CSR_MISA + GDB_REGNO_CSR0,
19-
GDB_REGNO_DPC = CSR_DPC + GDB_REGNO_CSR0,
20-
GDB_REGNO_DCSR = CSR_DCSR + GDB_REGNO_CSR0,
10+
GDB_REGNO_XPR31 = GDB_REGNO_XPR0 + 31,
11+
GDB_REGNO_PC = 32,
12+
GDB_REGNO_FPR0 = 33,
13+
GDB_REGNO_FPR31 = GDB_REGNO_FPR0 + 31,
14+
GDB_REGNO_CSR0 = 65,
15+
GDB_REGNO_TSELECT = CSR_TSELECT + GDB_REGNO_CSR0,
16+
GDB_REGNO_TDATA1 = CSR_TDATA1 + GDB_REGNO_CSR0,
17+
GDB_REGNO_TDATA2 = CSR_TDATA2 + GDB_REGNO_CSR0,
18+
GDB_REGNO_MISA = CSR_MISA + GDB_REGNO_CSR0,
19+
GDB_REGNO_DPC = CSR_DPC + GDB_REGNO_CSR0,
20+
GDB_REGNO_DCSR = CSR_DCSR + GDB_REGNO_CSR0,
2121
GDB_REGNO_DSCRATCH = CSR_DSCRATCH + GDB_REGNO_CSR0,
22-
GDB_REGNO_MSTATUS = CSR_MSTATUS + GDB_REGNO_CSR0,
23-
GDB_REGNO_CSR4095 = GDB_REGNO_CSR0 + 4095,
24-
GDB_REGNO_PRIV = 4161,
25-
GDB_REGNO_COUNT
22+
GDB_REGNO_MSTATUS = CSR_MSTATUS + GDB_REGNO_CSR0,
23+
GDB_REGNO_CSR4095 = GDB_REGNO_CSR0 + 4095,
24+
GDB_REGNO_PRIV = 4161,
25+
GDB_REGNO_COUNT
2626
};
2727

2828
#endif

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