@@ -1972,9 +1972,16 @@ static int deassert_reset(struct target *target)
19721972 return wait_for_state (target , TARGET_RUNNING );
19731973}
19741974
1975- static int read_memory (struct target * target , target_addr_t address ,
1976- uint32_t size , uint32_t count , uint8_t * buffer , uint32_t increment )
1975+ static int read_memory (struct target * target , const riscv_mem_access_args_t args )
19771976{
1977+ assert (riscv_mem_access_is_read (args ));
1978+
1979+ const target_addr_t address = args .address ;
1980+ const uint32_t size = args .size ;
1981+ const uint32_t count = args .count ;
1982+ const uint32_t increment = args .increment ;
1983+ uint8_t * const buffer = args .read_buffer ;
1984+
19781985 if (increment != size ) {
19791986 LOG_ERROR ("read_memory with custom increment not implemented" );
19801987 return ERROR_NOT_IMPLEMENTED ;
@@ -2142,9 +2149,20 @@ static int setup_write_memory(struct target *target, uint32_t size)
21422149 return ERROR_OK ;
21432150}
21442151
2145- static int write_memory (struct target * target , target_addr_t address ,
2146- uint32_t size , uint32_t count , const uint8_t * buffer )
2152+ static int write_memory (struct target * target , const riscv_mem_access_args_t args )
21472153{
2154+ assert (riscv_mem_access_is_write (args ));
2155+
2156+ if (args .increment != args .size ) {
2157+ LOG_TARGET_ERROR (target , "Write increment size has to be equal to element size" );
2158+ return ERROR_NOT_IMPLEMENTED ;
2159+ }
2160+
2161+ const target_addr_t address = args .address ;
2162+ const uint32_t size = args .size ;
2163+ const uint32_t count = args .count ;
2164+ const uint8_t * const buffer = args .write_buffer ;
2165+
21482166 riscv011_info_t * info = get_info (target );
21492167 jtag_add_ir_scan (target -> tap , & select_dbus , TAP_IDLE );
21502168
@@ -2371,7 +2389,9 @@ static int init_target(struct command_context *cmd_ctx,
23712389{
23722390 LOG_DEBUG ("init" );
23732391 RISCV_INFO (generic_info );
2392+ /* TODO: replace read and write with single access function*/
23742393 generic_info -> read_memory = read_memory ;
2394+ generic_info -> write_memory = write_memory ;
23752395 generic_info -> authdata_read = & riscv011_authdata_read ;
23762396 generic_info -> authdata_write = & riscv011_authdata_write ;
23772397 generic_info -> print_info = & riscv011_print_info ;
@@ -2406,7 +2426,5 @@ struct target_type riscv011_target = {
24062426 .assert_reset = assert_reset ,
24072427 .deassert_reset = deassert_reset ,
24082428
2409- .write_memory = write_memory ,
2410-
24112429 .arch_state = arch_state ,
24122430};
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