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target: align switch and case statements
The coding style requires the 'case' to be at the same indentation level of its 'switch' statement. Align the code accordingly. While there: - add space around the operators; - drop useless empty line. Skip all riscv code, as it is going to be updated soon from the external fork. No changes are reported by git log -p -w --ignore-blank-lines --patience Change-Id: I2691dfdd2b6734143e14160b46183623e9773539 Signed-off-by: Antonio Borneo <[email protected]> Reviewed-on: https://review.openocd.org/c/openocd/+/9051 Tested-by: jenkins
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41 files changed

+4201
-4206
lines changed

src/target/aarch64.c

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -613,22 +613,22 @@ static int aarch64_restore_one(struct target *target, bool current,
613613
* kill the return address
614614
*/
615615
switch (arm->core_state) {
616-
case ARM_STATE_ARM:
617-
resume_pc &= 0xFFFFFFFC;
618-
break;
619-
case ARM_STATE_AARCH64:
620-
resume_pc &= 0xFFFFFFFFFFFFFFFCULL;
621-
break;
622-
case ARM_STATE_THUMB:
623-
case ARM_STATE_THUMB_EE:
624-
/* When the return address is loaded into PC
625-
* bit 0 must be 1 to stay in Thumb state
626-
*/
627-
resume_pc |= 0x1;
628-
break;
629-
case ARM_STATE_JAZELLE:
630-
LOG_ERROR("How do I resume into Jazelle state??");
631-
return ERROR_FAIL;
616+
case ARM_STATE_ARM:
617+
resume_pc &= 0xFFFFFFFC;
618+
break;
619+
case ARM_STATE_AARCH64:
620+
resume_pc &= 0xFFFFFFFFFFFFFFFCULL;
621+
break;
622+
case ARM_STATE_THUMB:
623+
case ARM_STATE_THUMB_EE:
624+
/* When the return address is loaded into PC
625+
* bit 0 must be 1 to stay in Thumb state
626+
*/
627+
resume_pc |= 0x1;
628+
break;
629+
case ARM_STATE_JAZELLE:
630+
LOG_ERROR("How do I resume into Jazelle state??");
631+
return ERROR_FAIL;
632632
}
633633
LOG_DEBUG("resume pc = 0x%016" PRIx64, resume_pc);
634634
buf_set_u64(arm->pc->value, 0, 64, resume_pc);
@@ -3026,14 +3026,14 @@ COMMAND_HANDLER(aarch64_handle_disassemble_command)
30263026
target_addr_t address;
30273027

30283028
switch (CMD_ARGC) {
3029-
case 2:
3030-
COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
3031-
/* FALL THROUGH */
3032-
case 1:
3033-
COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
3034-
break;
3035-
default:
3036-
return ERROR_COMMAND_SYNTAX_ERROR;
3029+
case 2:
3030+
COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
3031+
/* FALL THROUGH */
3032+
case 1:
3033+
COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
3034+
break;
3035+
default:
3036+
return ERROR_COMMAND_SYNTAX_ERROR;
30373037
}
30383038

30393039
return a64_disassemble(CMD, target, address, count);

src/target/arc.c

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1892,18 +1892,18 @@ static int arc_set_watchpoint(struct target *target,
18921892

18931893
int enable = AP_AC_TT_DISABLE;
18941894
switch (watchpoint->rw) {
1895-
case WPT_READ:
1896-
enable = AP_AC_TT_READ;
1897-
break;
1898-
case WPT_WRITE:
1899-
enable = AP_AC_TT_WRITE;
1900-
break;
1901-
case WPT_ACCESS:
1902-
enable = AP_AC_TT_READWRITE;
1903-
break;
1904-
default:
1905-
LOG_TARGET_ERROR(target, "BUG: watchpoint->rw neither read, write nor access");
1906-
return ERROR_FAIL;
1895+
case WPT_READ:
1896+
enable = AP_AC_TT_READ;
1897+
break;
1898+
case WPT_WRITE:
1899+
enable = AP_AC_TT_WRITE;
1900+
break;
1901+
case WPT_ACCESS:
1902+
enable = AP_AC_TT_READWRITE;
1903+
break;
1904+
default:
1905+
LOG_TARGET_ERROR(target, "BUG: watchpoint->rw neither read, write nor access");
1906+
return ERROR_FAIL;
19071907
}
19081908

19091909
int retval = arc_configure_actionpoint(target, wp_num,

src/target/arc_cmd.c

Lines changed: 23 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -709,29 +709,29 @@ COMMAND_HANDLER(arc_handle_get_reg_field)
709709
int retval = arc_reg_get_field(target, reg_name, field_name, &value);
710710

711711
switch (retval) {
712-
case ERROR_OK:
713-
break;
714-
case ERROR_ARC_REGISTER_NOT_FOUND:
715-
command_print(CMD,
716-
"Register `%s' has not been found.", reg_name);
717-
return ERROR_COMMAND_ARGUMENT_INVALID;
718-
case ERROR_ARC_REGISTER_IS_NOT_STRUCT:
719-
command_print(CMD,
720-
"Register `%s' must have 'struct' type.", reg_name);
721-
return ERROR_COMMAND_ARGUMENT_INVALID;
722-
case ERROR_ARC_REGISTER_FIELD_NOT_FOUND:
723-
command_print(CMD,
724-
"Field `%s' has not been found in register `%s'.",
725-
field_name, reg_name);
726-
return ERROR_COMMAND_ARGUMENT_INVALID;
727-
case ERROR_ARC_FIELD_IS_NOT_BITFIELD:
728-
command_print(CMD,
729-
"Field `%s' is not a 'bitfield' field in a structure.",
730-
field_name);
731-
return ERROR_COMMAND_ARGUMENT_INVALID;
732-
default:
733-
/* Pass through other errors. */
734-
return retval;
712+
case ERROR_OK:
713+
break;
714+
case ERROR_ARC_REGISTER_NOT_FOUND:
715+
command_print(CMD,
716+
"Register `%s' has not been found.", reg_name);
717+
return ERROR_COMMAND_ARGUMENT_INVALID;
718+
case ERROR_ARC_REGISTER_IS_NOT_STRUCT:
719+
command_print(CMD,
720+
"Register `%s' must have 'struct' type.", reg_name);
721+
return ERROR_COMMAND_ARGUMENT_INVALID;
722+
case ERROR_ARC_REGISTER_FIELD_NOT_FOUND:
723+
command_print(CMD,
724+
"Field `%s' has not been found in register `%s'.",
725+
field_name, reg_name);
726+
return ERROR_COMMAND_ARGUMENT_INVALID;
727+
case ERROR_ARC_FIELD_IS_NOT_BITFIELD:
728+
command_print(CMD,
729+
"Field `%s' is not a 'bitfield' field in a structure.",
730+
field_name);
731+
return ERROR_COMMAND_ARGUMENT_INVALID;
732+
default:
733+
/* Pass through other errors. */
734+
return retval;
735735
}
736736

737737
command_print(CMD, "0x%" PRIx32, value);

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