[ACT] [CTG] [ISAC] Add support Zcd extension in RV64 (#587)

* Updated Zcf and Zcd test case

* Updated Zcf and Zcd instruction support with respect to riscv-ctg and riscv-isac

* Added test cases for RV64Zcd

---------

Signed-off-by: anuani21 <[email protected]>
Co-authored-by: James Shi <[email protected]>

Author: anuani21

riscv-test-suite/rv64i_m/D_Zcd/src/c.fld-01.S

@@ -0,0 +1,173 @@
+
+// -----------
+// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
+// version   : 0.11.0
+// timestamp : Wed Aug 16 05:06:00 2023 GMT
+// usage     : riscv_ctg \
+//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fld.cgf \
+ \
+//                  -- xlen 64  \
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.fld instruction of the RISC-V RV64FDC extension for the c.fld covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IFDC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fld)
+
+RVTEST_FP_ENABLE()
+RVTEST_VALBASEUPD(x3,test_dataset_0)
+RVTEST_SIGBASE(x1,signature_x1_1)
+
+inst_0:
+// rs1 != rd, rs1==x15, rd==f15,imm_val == 0 and fcsr == 0, 
+// opcode:c.fld; op1:x15; dest:f15; immval:0x0; align:0; flagreg:x4
+TEST_LOAD_F(x1,x2,0,x15,f15,0x0,c.fld,0,x4)
+
+inst_1:
+// rs1==x14, rd==f14,imm_val > 0  and fcsr == 0, 
+// opcode:c.fld; op1:x14; dest:f14; immval:0xf8; align:0; flagreg:x4
+TEST_LOAD_F(x1,x2,0,x14,f14,0xf8,c.fld,0,x4)
+
+inst_2:
+// rs1==x13, rd==f13,imm_val == 168, 
+// opcode:c.fld; op1:x13; dest:f13; immval:0xa8; align:0; flagreg:x4
+TEST_LOAD_F(x1,x2,159,x13,f13,0xa8,c.fld,0,x4)
+
+inst_3:
+// rs1==x12, rd==f12,imm_val == 80, 
+// opcode:c.fld; op1:x12; dest:f12; immval:0x50; align:0; flagreg:x4
+TEST_LOAD_F(x1,x2,159,x12,f12,0x50,c.fld,0,x4)
+
+inst_4:
+// rs1==x11, rd==f11,imm_val == 8, 
+// opcode:c.fld; op1:x11; dest:f11; immval:0x8; align:0; flagreg:x4
+TEST_LOAD_F(x1,x2,159,x11,f11,0x8,c.fld,0,x4)
+
+inst_5:
+// rs1==x10, rd==f10,imm_val == 16, 
+// opcode:c.fld; op1:x10; dest:f10; immval:0x10; align:0; flagreg:x4
+TEST_LOAD_F(x1,x2,159,x10,f10,0x10,c.fld,0,x4)
+
+inst_6:
+// rs1==x9, rd==f9,imm_val == 240, 
+// opcode:c.fld; op1:x9; dest:f9; immval:0xf0; align:0; flagreg:x4
+TEST_LOAD_F(x1,x2,159,x9,f9,0xf0,c.fld,0,x4)
+
+inst_7:
+// rs1==x8, rd==f8,imm_val == 232, 
+// opcode:c.fld; op1:x8; dest:f8; immval:0xe8; align:0; flagreg:x4
+TEST_LOAD_F(x1,x2,159,x8,f8,0xe8,c.fld,0,x4)
+
+inst_8:
+// imm_val == 216, 
+// opcode:c.fld; op1:x15; dest:f15; immval:0xd8; align:0; flagreg:x4
+TEST_LOAD_F(x1,x2,159,x15,f15,0xd8,c.fld,0,x4)
+
+inst_9:
+// imm_val == 184, 
+// opcode:c.fld; op1:x15; dest:f15; immval:0xb8; align:0; flagreg:x4
+TEST_LOAD_F(x1,x2,159,x15,f15,0xb8,c.fld,0,x4)
+
+inst_10:
+// imm_val == 120, 
+// opcode:c.fld; op1:x15; dest:f15; immval:0x78; align:0; flagreg:x4
+TEST_LOAD_F(x1,x2,159,x15,f15,0x78,c.fld,0,x4)
+
+inst_11:
+// imm_val == 32, 
+// opcode:c.fld; op1:x15; dest:f15; immval:0x20; align:0; flagreg:x4
+TEST_LOAD_F(x1,x2,159,x15,f15,0x20,c.fld,0,x4)
+
+inst_12:
+// imm_val == 64, 
+// opcode:c.fld; op1:x15; dest:f15; immval:0x40; align:0; flagreg:x4
+TEST_LOAD_F(x1,x2,159,x15,f15,0x40,c.fld,0,x4)
+
+inst_13:
+// imm_val == 128, 
+// opcode:c.fld; op1:x15; dest:f15; immval:0x80; align:0; flagreg:x4
+TEST_LOAD_F(x1,x2,159,x15,f15,0x80,c.fld,0,x4)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+.word 0xabecafeb
+.word 0xbecafeba
+.word 0xecafebab
+test_dataset_0:
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+rvtest_sig_begin:
+sig_begin_canary:
+CANARY;
+
+
+
+signature_x1_0:
+    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 28*((SIGALIGN)/4),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+tsig_begin_canary:
+CANARY;
+
+mtrap_sigptr:
+    .fill 64*XLEN/32,4,0xdeadbeef
+
+tsig_end_canary:
+CANARY;
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*XLEN/32,4,0xdeadbeef
+
+#endif
+
+
+sig_end_canary:
+CANARY;
+rvtest_sig_end:
+RVMODEL_DATA_END