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1 parent a128983 commit 97a9ec6Copy full SHA for 97a9ec6
riscv-elf.md
@@ -434,6 +434,9 @@ rules about 2✕XLEN aligned arguments being passed in "aligned" register pairs.
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store "float" and "double" values in F registers, but would not store "long
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double" values in F registers. If none of the float ABI flags are set, the
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object is taken to use the soft-float ABI.
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+ * EF_RISCV_FLOAT_ABI (0x0006): This macro is used as a mask to test for one
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+ of the above floating-point ABIs, e.g.,
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+ `(e_flags & EF_RISCV_FLOAT_ABI) == EF_RISCV_FLOAT_ABI_DOUBLE`.
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* EF_RISCV_RVE (0x0008): This bit is set when the binary targets the E ABI.
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* EF_RISCV_TSO (0x0010): This bit is set when the binary requires the RVTSO
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memory consistency model.
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