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This is a change suggested in ARC feedback. Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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| such differences do not interfere with architectural state migration | ||
| and subsequent execution of threads between harts. | ||
| 2+a| _Architectural state comprises all ISA-visible state relevant to | ||
| the SEE, including but not limited to: XLEN, endianness, |
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Please, add VLEN to the enumerated properties.
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| _Prohibited divergences (non-exhaustive):_ | ||
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| * _Differences in XLEN, endianness, mandatory privilege features, or |
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Please, add VLEN to the enumerated properties.
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| such differences do not interfere with architectural state migration | ||
| and subsequent execution of threads between harts. | ||
| 2+a| _Architectural state comprises all ISA-visible state relevant to | ||
| the SEE, including but not limited to: XLEN, endianness, |
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| the SEE, including but not limited to: XLEN, endianness, | |
| the SEE, including but not limited to: XLEN, VLEN, cache block size, endianness, |
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server_platform_requirements.adoc
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| _Prohibited divergences (non-exhaustive):_ | ||
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| * _Differences in XLEN, endianness, mandatory privilege features, or |
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Suggested change
| * _Differences in XLEN, endianness, mandatory privilege features, or | |
| * _Differences in XLEN, VLEN, endianness, cache block sizes, mandatory privilege features, or |
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November 24, 2025 14:42
This is a changed suggested in ARC feedback. The new text was provided by ARC. Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
This is a change suggested in ARC feedback. From Ved: """ The debug related registers to setup triggers are not visible to ISA. The RVA_060 and RVA_070 are discussing that. The Sdext and Sdtrig - the parts of debug that are visible to S-mode - are included in RVA020. I would suggest a section called "RISC-V Hart SEE" and place the RVA_060 and RVA_070 in that section. """ Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Now that two rules have been moved out of the section, renumber to regain an even distribution. Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
This is a change suggested in ARC feedback. From Ved: """ Update RVA_070 to make filtering by ASID/VMID required and scontext/hcontext optional - presently the rule states either may be implemented but neither are required. """ Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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I've add VLEN and cache block sizes. Do we still need to also call out the memory map as @radimkrcmar suggested? |
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