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Clarifying supervisor execution environment requirements.#96

Merged
jones-drew merged 3 commits intoriscv-non-isa:mainfrom
radimkrcmar:merge-rva_040
Sep 30, 2025
Merged

Clarifying supervisor execution environment requirements.#96
jones-drew merged 3 commits intoriscv-non-isa:mainfrom
radimkrcmar:merge-rva_040

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@radimkrcmar
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The beef of this series is the third patch. The general goal is to make SEE a bit clearer, but the tools to model what is indistinguishable from a software execution viewpoint are not really in place, so the rule leaves most of the actual requirements to reader's imagination (and non-normative text).

The profile status of implemented extensions is irrelevant.
The original was too focused on CSR fields widths, which is a subset of
CSR legal values.  And we're not even limiting the definition to CSRs,
as cache block sizes are mentioned among the examples.
Copilot AI review requested due to automatic review settings September 30, 2025 14:58
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Pull Request Overview

This PR clarifies the requirements for supervisor execution environment (SEE) by consolidating and refactoring the rules for RISC-V application processor harts. The changes aim to make the concept of "indistinguishable from a software execution viewpoint" clearer while acknowledging the inherent vagueness of this requirement.

  • Merged RVA_040 and RVA_050 into a single, more comprehensive rule
  • Expanded the explanation to cover ISA extensions, non-ISA extensions, memory address spaces, and allowable differences
  • Added explicit acknowledgment that the rule is intentionally vague but captures the spirit of task migration requirements

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The harts may support different power and performance characteristics.
The harts may have different microarchitecture identifiers (mvendorid,
marchid, and mimpid), and any other identifiers.
This rule is vague on purpose, and tries to capture the spirit of the
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[nitpick] The phrase 'vague on purpose' in formal specification documentation may confuse readers. Consider rephrasing to something like 'This rule is intentionally high-level' or 'This rule provides general guidance' to maintain professional tone while acknowledging the broad nature of the requirement.

Suggested change
This rule is vague on purpose, and tries to capture the spirit of the
This rule is intentionally high-level and is intended to capture the spirit of the

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Suggested change
This rule is vague on purpose, and tries to capture the spirit of the
This rule addresses the following goal:

RVA_050 is a strict superset of RVA_040, which created confusion about
the purpose of RVA_040.  Merge both of them into RVA_040, and expand the
non-normative notes to cover cases from both.
@radimkrcmar radimkrcmar force-pushed the merge-rva_040 branch 2 times, most recently from 42c1cae to b7d0aeb Compare September 30, 2025 15:41
@jones-drew jones-drew merged commit 420e31d into riscv-non-isa:main Sep 30, 2025
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3 participants