Merge pull request #2013 from binno/aia_fix

Ensure AIA extension enabled when accessing hvictl

Author: aswaterman

riscv/csrs.cc

@@ -890,9 +890,11 @@ mip_proxy_csr_t::mip_proxy_csr_t(processor_t* const proc, const reg_t addr, gene
 
 void mip_proxy_csr_t::verify_permissions(insn_t insn, bool write) const {
   csr_t::verify_permissions(insn, write);
-  if ((state->csrmap[CSR_HVICTL]->read() & HVICTL_VTI) &&
-      proc->extension_enabled('S') && state->v)
-    throw trap_virtual_instruction(insn.bits()); // VS-mode attempts to access sip when hvictl.VTI=1
+  if (proc->extension_enabled_const(EXT_SSAIA) && proc->extension_enabled('H')) {
+    if ((state->csrmap[CSR_HVICTL]->read() & HVICTL_VTI) &&
+        proc->extension_enabled('S') && state->v)
+      throw trap_virtual_instruction(insn.bits()); // VS-mode attempts to access sip when hvictl.VTI=1
+  }
 }
 
 reg_t mip_proxy_csr_t::read() const noexcept {
@@ -912,9 +914,11 @@ mie_proxy_csr_t::mie_proxy_csr_t(processor_t* const proc, const reg_t addr, gene
 
 void mie_proxy_csr_t::verify_permissions(insn_t insn, bool write) const {
   csr_t::verify_permissions(insn, write);
-  if ((state->csrmap[CSR_HVICTL]->read() & HVICTL_VTI) &&
-      proc->extension_enabled('S') && state->v)
-    throw trap_virtual_instruction(insn.bits()); // VS-mode attempts to access sie when hvictl.VTI=1
+  if (proc->extension_enabled_const(EXT_SSAIA) && proc->extension_enabled('H')) {
+    if ((state->csrmap[CSR_HVICTL]->read() & HVICTL_VTI) &&
+        proc->extension_enabled('S') && state->v)
+      throw trap_virtual_instruction(insn.bits()); // VS-mode attempts to access sie when hvictl.VTI=1
+  }
 }
 
 reg_t mie_proxy_csr_t::read() const noexcept {
@@ -1731,8 +1735,10 @@ void stimecmp_csr_t::verify_permissions(insn_t insn, bool write) const {
 
   basic_csr_t::verify_permissions(insn, write);
 
-  if ((state->csrmap[CSR_HVICTL]->read() & HVICTL_VTI) && state->v && write)
-    throw trap_virtual_instruction(insn.bits());
+  if (proc->extension_enabled_const(EXT_SSAIA) && proc->extension_enabled('H')) {
+    if ((state->csrmap[CSR_HVICTL]->read() & HVICTL_VTI) && state->v && write)
+      throw trap_virtual_instruction(insn.bits());
+  }
 }
 
 virtualized_with_special_permission_csr_t::virtualized_with_special_permission_csr_t(processor_t* const proc, csr_t_p orig, csr_t_p virt):