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Pull requests: riscv-software-src/riscv-isa-sim

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Pull requests list

correct smcdeleg indirect CSRs address accessed via sireg* and fix mevent[n] indirect access with Smcdeleg/Ssccfg/Zihpm/Sscofpmf
#2205 opened Jan 3, 2026 by Steven-Li-Xiaogang Loading…
Add support for per-hart start PCs (--pc-harts)
#2199 opened Dec 30, 2025 by nabudahab Loading…
Fix triggers for accesses wider than XLEN
#2198 opened Dec 27, 2025 by aswaterman Loading…
Implemented the ability to execute any postprocess provided by the plugin after each instruction
#2172 opened Dec 2, 2025 by kseniadobrovolskaya Loading…
6
Feature proposal POC: DTB discovery feature
#2165 opened Nov 27, 2025 by FrancescoScappatura-Ax Loading…
FP8 support
#2118 opened Oct 31, 2025 by A-Marcelli Loading…
5
Support label-based sideband commands for printing register contents
#2024 opened Jul 2, 2025 by maerhart Loading…
Implement IMSIC and APLIC
#1999 opened Jun 6, 2025 by i2h2 Loading…
13
Add feature Smcdeleg
#1913 opened Feb 7, 2025 by JJ-Gaisler Loading…
5
8 bit floating point
#1910 opened Feb 6, 2025 by rbuchner-aril Loading…
2
Fix envcfg check when S-mode is not available
#1899 opened Jan 21, 2025 by mimiqdev Loading…
1
2
Adding version display option with --version
#1897 opened Jan 20, 2025 by ahmedelalfy94 Loading…
5
Smcsrind exception fixex
#1896 opened Jan 20, 2025 by JJ-Gaisler Loading…
6
Fix read value of CSR mip.
#1869 opened Dec 9, 2024 by NewPaulWalker Loading…
6
Add Shlcofideleg support
#1847 opened Oct 31, 2024 by demin-han Loading…
2
ADD: a basic BTM N-trace spec compliant trace encoder model
#1824 opened Sep 30, 2024 by iansseijelly Loading…
26
Fix vleff: reduce VL if trigger fired on a later element.
#1818 opened Sep 26, 2024 by NewPaulWalker Loading…
Fix dtc_output read when interrupted by EINTR
#1801 opened Sep 10, 2024 by MarcoBonino Loading…
3
README.md: update "Debugging With Gdb"
#1800 opened Sep 9, 2024 by hirooih Loading…
Check tcontrol.mte in trigger_t::allow_action()
#1777 opened Aug 16, 2024 by rtwfroody Loading…
15
Vector crypto additional
#1748 opened Jul 25, 2024 by nibrunieAtSi5 • Draft
medeleg: the third bit(CAUSE_BREAKPOINT) of medeleg is unwritable when Sdtrig exist.
#1742 opened Jul 23, 2024 by NewPaulWalker Loading…
6
hvip: Correct logging value of mip on writing hvip
#1741 opened Jul 23, 2024 by YenHaoChen Loading…
Update mcontrol6 to support version 1.0
#1667 opened May 14, 2024 by rtwfroody Loading…
4
don't read CSR in csrrw(i) with rd=0
#1628 opened Mar 19, 2024 by ShengMingTangAndes Loading…
1
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