Add dtb_discovery ci-tests

FrancescoScappatura-Ax · FrancescoScappatura-Ax · commit 139b4b88dc56 · 2026-02-13T11:27:59.000+01:00
diff --git a/ci-tests/dtb-discovery/devices-sample/led-device.cc b/ci-tests/dtb-discovery/devices-sample/led-device.cc
@@ -0,0 +1,99 @@
+#include "led-device.h"
+#include <cstring>
+#include <cstdio>
+#include <sstream>
+#include <algorithm>
+
+led_device_t::led_device_t(const sim_t *sim, reg_t base, size_t size, uint32_t num_leds)
+    : sim(sim), base_addr(base), dev_size(size), 
+      num_leds(std::min(num_leds, 32u)), led_state(0) {
+  printf("LED device init at 0x%lx, size: 0x%lx, num_leds: %u\n", 
+         base_addr, dev_size, this->num_leds);
+}
+
+bool led_device_t::load(reg_t addr, size_t len, uint8_t* bytes) {
+  printf("led_device_t::load from address: 0x%lx, length: %zu\n",
+         base_addr + addr, len);
+  
+  if (addr == 0 && len == 4) {
+    uint32_t masked_state = led_state & ((1u << num_leds) - 1);
+    memcpy(bytes, &masked_state, 4);
+    return true;
+  }
+  return false;
+}
+
+bool led_device_t::store(reg_t addr, size_t len, const uint8_t* bytes) {
+  printf("led_device_t::store to address: 0x%lx, length: %zu\n",
+         base_addr + addr, len);
+  
+  if (addr == 0 && len == 4) {
+    uint32_t new_state;
+    memcpy(&new_state, bytes, 4);
+    led_state = new_state & ((1u << num_leds) - 1);
+    
+    printf("LED state changed to: 0x%x\n", led_state);
+    printf("LED pattern (%u LEDs): ", num_leds);
+    for (int i = num_leds - 1; i >= 0; i--) {
+      printf("%c", (led_state & (1 << i)) ? ' ' : '-');
+    }
+    printf(" (0x%x)\n", led_state);
+    return true;
+  }
+  return false;
+}
+
+size_t led_device_t::size() {
+  return dev_size;
+}
+
+led_device_t* led_parse_from_fdt(const void *fdt, const sim_t *sim,
+                                 reg_t *base, std::vector<std::string> args) {
+  if (args.size() < 3) {
+    fprintf(stderr, "Error: led device requires 3 arguments (base, size, num_leds)\n");
+    return nullptr;
+  }
+  
+  try {
+    *base = std::stoull(args[0], nullptr, 0);
+    reg_t size = std::stoull(args[1], nullptr, 0);
+    uint32_t num_leds = std::stoul(args[2], nullptr, 0);
+    
+    if (num_leds == 0 || num_leds > 32) {
+      fprintf(stderr, "Error: num_leds must be between 1 and 32, got %u\n", num_leds);
+      return nullptr;
+    }
+    
+    return new led_device_t(sim, *base, size, num_leds);
+  } catch (const std::exception& e) {
+    fprintf(stderr, "Error parsing LED device params: %s\n", e.what());
+    return nullptr;
+  }
+}
+
+std::string led_generate_dts(const sim_t *sim, const std::vector<std::string> &args) {
+  std::ostringstream s;
+  reg_t base = 0x10001000;
+  reg_t size = 0x1000;
+  uint32_t num_leds = 8;
+  
+  if (args.size() >= 3) {
+    base = std::stoull(args[0], nullptr, 0);
+    size = std::stoull(args[1], nullptr, 0);
+    num_leds = std::stoul(args[2], nullptr, 0);
+  }
+  
+  s << std::hex
+    << "    led@" << base << " {\n"
+    << "      compatible = \"led\";\n"
+    << "      reg = <0x0 0x" << base << " 0x0 0x" << size << ">;\n"
+    << std::dec
+    << "      num-leds = <" << num_leds << ">;\n"
+    << std::hex
+    << "      spike,plugin-params = \"0x" << base << ",0x" << size << "," << std::dec << num_leds << "\";\n"
+    << "    };\n";
+  
+  return s.str();
+}
+
+REGISTER_DEVICE(led_device, led_parse_from_fdt, led_generate_dts)
diff --git a/ci-tests/dtb-discovery/devices-sample/led-device.h b/ci-tests/dtb-discovery/devices-sample/led-device.h
@@ -0,0 +1,26 @@
+#ifndef LED_DEVICE_H
+#define LED_DEVICE_H
+
+#include <riscv/sim.h>
+#include <vector>
+#include <string>
+
+class led_device_t : public abstract_device_t {
+public:
+  led_device_t(const sim_t *sim, reg_t base, size_t size, uint32_t num_leds);
+  
+  bool load(reg_t addr, size_t len, uint8_t* bytes) override;
+  bool store(reg_t addr, size_t len, const uint8_t* bytes) override;
+  size_t size() override;
+  
+private:
+  const sim_t *sim;
+  reg_t base_addr;
+  size_t dev_size;
+  uint32_t num_leds;
+  uint32_t led_state;
+};
+
+ 
+
+#endif // LED_DEVICE_H
diff --git a/ci-tests/dtb-discovery/dts-samples/devices-clint-plic-uart.dts b/ci-tests/dtb-discovery/dts-samples/devices-clint-plic-uart.dts
@@ -0,0 +1,52 @@
+/dts-v1/;
+/ {
+    #address-cells = <2>;
+    #size-cells = <2>;
+    
+    cpus {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        timebase-frequency = <10000000>;
+        
+        CPU0: cpu@0 {
+            device_type = "cpu";
+            reg = <0>;
+            riscv,isa = "rv64imafdc";
+            
+            CPU0_intc: interrupt-controller {
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                compatible = "riscv,cpu-intc";
+            };
+        };
+    };
+    
+    memory@90000000 {
+        device_type = "memory";
+        reg = <0x00000000 0x90000000 0x00000000 0x10000000>;  
+    };
+
+    clint@2000000 {
+        compatible = "riscv,clint0";
+        reg = <0x0 0x2000000 0x0 0xc0000>;
+    };
+    
+    PLIC: plic@c000000 {
+        compatible = "riscv,plic0";
+        reg = <0x0 0xc000000 0x0 0x1000000>;
+        riscv,ndev = <0x1f>;
+        riscv,max-priority = <0xf>;
+        #interrupt-cells = <1>;
+        interrupt-controller;
+    };
+
+    uart0: serial@10000000 {
+        compatible = "ns16550a";
+        reg = <0x0 0x10000000 0x0 0x100>;
+        clock-frequency = <10000000>;
+        interrupts = <10>;
+        reg-shift = <0>;
+        reg-io-width = <1>;
+    };
+    
+};
diff --git a/ci-tests/dtb-discovery/dts-samples/devices-multiple-leds.dts b/ci-tests/dtb-discovery/dts-samples/devices-multiple-leds.dts
@@ -0,0 +1,36 @@
+/dts-v1/;
+
+/ {
+    #address-cells = <2>;
+    #size-cells = <2>;
+    
+    cpus {  // Container for all CPU cores
+      #address-cells = <1>;  // CPU children use 1 cell for hartid
+      #size-cells = <0>;     // CPU children don't specify size
+      timebase-frequency = <10000000>;  // Timer ticks at 10 MHz (for OS timing)
+      
+      CPU0: cpu@0 {  // First CPU core (label: CPU0, unit address: 0)
+        device_type = "cpu";  // Identifies this as a CPU device
+        reg = <0>;            // Hartid = 0 (hardware thread ID)
+        riscv,isa = "rv64imafdc";  // ISA: RV64 with I,M,A,F,D,C extensions
+      };
+    };
+
+
+    memory@90000000 {
+        device_type = "memory";
+        reg = <0x0 0x90000000 0x0 0x00010000>;
+    };
+
+    led1@10001000 {
+        compatible = "led_device";
+        reg = <0x0 0x10001000 0x0 0x1000>;
+        spike,plugin-params = "16";
+    };
+
+    led2@10002000 {
+        compatible = "led_device";
+        reg = <0x0 0x10002000 0x0 0x1000>;
+        spike,plugin-params = "8";
+    };
+};
diff --git a/ci-tests/dtb-discovery/dts-samples/devices-single-led.dts b/ci-tests/dtb-discovery/dts-samples/devices-single-led.dts
@@ -0,0 +1,26 @@
+/dts-v1/;
+
+/ {
+    #address-cells = <2>;
+    #size-cells = <2>;
+
+    cpus {  // Container for all CPU cores
+      #address-cells = <1>;  // CPU children use 1 cell for hartid
+      #size-cells = <0>;     // CPU children don't specify size
+      timebase-frequency = <10000000>;  // Timer ticks at 10 MHz (for OS timing)
+      
+      CPU0: cpu@0 {  // First CPU core (label: CPU0, unit address: 0)
+        device_type = "cpu";  // Identifies this as a CPU device
+        reg = <0>;            // Hartid = 0 (hardware thread ID)
+        riscv,isa = "rv64imafdc";  // ISA: RV64 with I,M,A,F,D,C extensions
+      };
+    };
+
+
+    led@10001000 {
+        compatible = "led_device";
+        reg = <0x0 0x10001000 0x0 0x00001000>;
+        spike,plugin-params = "16";
+    };
+ 
+};
diff --git a/ci-tests/dtb-discovery/dts-samples/mem-32bit.dts b/ci-tests/dtb-discovery/dts-samples/mem-32bit.dts
@@ -0,0 +1,23 @@
+/dts-v1/;
+/ {
+    #address-cells = <1>;
+    #size-cells = <1>;
+
+    cpus {  // Container for all CPU cores
+      #address-cells = <1>;  // CPU children use 1 cell for hartid
+      #size-cells = <0>;     // CPU children don't specify size
+      timebase-frequency = <10000000>;  // Timer ticks at 10 MHz (for OS timing)
+      
+      CPU0: cpu@0 {  // First CPU core (label: CPU0, unit address: 0)
+        device_type = "cpu";  // Identifies this as a CPU device
+        reg = <0>;            // Hartid = 0 (hardware thread ID)
+        riscv,isa = "rv64imafdc";  // ISA: RV64 with I,M,A,F,D,C extensions
+      };
+    };
+
+
+    memory@80000000 {
+        device_type = "memory";
+        reg = <0x80000000 0x10000000>; // 256MB
+    };
+};
diff --git a/ci-tests/dtb-discovery/dts-samples/mem-64bit-single.dts b/ci-tests/dtb-discovery/dts-samples/mem-64bit-single.dts
@@ -0,0 +1,24 @@
+/dts-v1/;
+/ {
+    #address-cells = <2>;
+    #size-cells = <2>;
+
+    cpus {  // Container for all CPU cores
+      #address-cells = <1>;  // CPU children use 1 cell for hartid
+      #size-cells = <0>;     // CPU children don't specify size
+      timebase-frequency = <10000000>;  // Timer ticks at 10 MHz (for OS timing)
+      
+      CPU0: cpu@0 {  // First CPU core (label: CPU0, unit address: 0)
+        device_type = "cpu";  // Identifies this as a CPU device
+        reg = <0>;            // Hartid = 0 (hardware thread ID)
+        riscv,isa = "rv64imafdc";  // ISA: RV64 with I,M,A,F,D,C extensions
+      };
+    };
+
+
+    memory@80000000 {
+        device_type = "memory";
+        reg = <0x0 0x20000000  0x0 0x40000000>; // 1GB
+    };
+};
+
diff --git a/ci-tests/dtb-discovery/dts-samples/mem-mixed-cells-sizes.dts b/ci-tests/dtb-discovery/dts-samples/mem-mixed-cells-sizes.dts
@@ -0,0 +1,23 @@
+/dts-v1/;
+/ {
+    #address-cells = <2>;
+    #size-cells = <1>;
+
+    cpus {  // Container for all CPU cores
+      #address-cells = <1>;  // CPU children use 1 cell for hartid
+      #size-cells = <0>;     // CPU children don't specify size
+      timebase-frequency = <10000000>;  // Timer ticks at 10 MHz (for OS timing)
+      
+      CPU0: cpu@0 {  // First CPU core (label: CPU0, unit address: 0)
+        device_type = "cpu";  // Identifies this as a CPU device
+        reg = <0>;            // Hartid = 0 (hardware thread ID)
+        riscv,isa = "rv64imafdc";  // ISA: RV64 with I,M,A,F,D,C extensions
+      };
+    };
+
+
+    memory@100000000 {
+        device_type = "memory";
+        reg = <0x1 0x00000000  0x20000000>; // 512MB at 4GB
+    };
+};
diff --git a/ci-tests/dtb-discovery/dts-samples/mem-multiple-nodes.dts b/ci-tests/dtb-discovery/dts-samples/mem-multiple-nodes.dts
@@ -0,0 +1,28 @@
+/dts-v1/;
+/ {
+    #address-cells = <2>;
+    #size-cells = <2>;
+
+    cpus {  // Container for all CPU cores
+      #address-cells = <1>;  // CPU children use 1 cell for hartid
+      #size-cells = <0>;     // CPU children don't specify size
+      timebase-frequency = <10000000>;  // Timer ticks at 10 MHz (for OS timing)
+      
+      CPU0: cpu@0 {  // First CPU core (label: CPU0, unit address: 0)
+        device_type = "cpu";  // Identifies this as a CPU device
+        reg = <0>;            // Hartid = 0 (hardware thread ID)
+        riscv,isa = "rv64imafdc";  // ISA: RV64 with I,M,A,F,D,C extensions
+      };
+    };
+
+
+    memory@80000000 {
+        device_type = "memory";
+        reg = <0x0 0x80000000 0x0 0x20000000>;
+    };
+
+    memory@A0000000 {
+        device_type = "memory";
+        reg = <0x0 0xA0000000 0x0 0x20000000>;
+    };
+};
diff --git a/ci-tests/dtb-discovery/test-dtb-discovery.cc b/ci-tests/dtb-discovery/test-dtb-discovery.cc
diff --git a/ci-tests/test-spike b/ci-tests/test-spike
