Merge pull request #2101 from sifive/master

Add Zvfbfa, Zvfofp8min, Zvfofp4min support

Author: aswaterman

disasm/disasm.cc

@@ -1973,6 +1973,16 @@ void disassembler_t::add_instructions(const isa_parser_t* isa, bool strict)
     #undef DISASM_VFUNARY0_INSN
   }
 
+  if (ext_enabled(EXT_ZVFOFP4MIN)) {
+    DEFINE_VECTOR_V(vfext_vf2);
+  }
+
+  if (ext_enabled(EXT_ZVFOFP8MIN)) {
+    DEFINE_VECTOR_V(vfncvt_f_f_q);
+    DEFINE_VECTOR_V(vfncvt_sat_f_f_q);
+    DEFINE_VECTOR_V(vfncvtbf16_sat_f_f_w);
+  }
+
   if (ext_enabled(EXT_ZVFBFMIN)) {
     DEFINE_VECTOR_V(vfncvtbf16_f_f_w);
     DEFINE_VECTOR_V(vfwcvtbf16_f_f_v);

disasm/isa_parser.cc

@@ -130,6 +130,12 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv)
         // Zvfh implies Zfhmin
         extension_table[EXT_ZFHMIN] = true;
       }
+    } else if (ext_str == "zvfbfa") {
+      extension_table[EXT_ZVFBFA] = true;
+    } else if (ext_str == "zvfofp4min") {
+      extension_table[EXT_ZVFOFP4MIN] = true;
+    } else if (ext_str == "zvfofp8min") {
+      extension_table[EXT_ZVFOFP8MIN] = true;
     } else if (ext_str == "zicsr") {
       // Spike necessarily has Zicsr, because
       // Zicsr is implied by the privileged architecture
@@ -481,10 +487,22 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv)
     bad_isa_string(str, "'Zvfbfmin' extension requires 'Zve32f' extension");
   }
 
+  if (extension_table[EXT_ZVFBFA] && (!has_any_vector() || !extension_table[EXT_ZFBFMIN] || !get_zvf())) {
+    bad_isa_string(str, "'zvfbfa' extension requires at least 'Zve32f', and 'Zfbfmin'");
+  }
+
   if (extension_table[EXT_ZVFBFWMA] && (!extension_table[EXT_ZFBFMIN] || !extension_table[EXT_ZVFBFMIN])) {
     bad_isa_string(str, "'Zvfbfwma' extension requires 'Zfbfmin' and 'Zvfbfmin' extensions");
   }
 
+  if (extension_table[EXT_ZVFOFP4MIN] && (!has_any_vector() || !get_zvf())) {
+    bad_isa_string(str, "'Zvfofp4min' extension requires either 'V' or 'Zve32f' extension");
+  }
+
+  if (extension_table[EXT_ZVFOFP8MIN] && (!has_any_vector() || !get_zvf())) {
+    bad_isa_string(str, "'Zvfofp8min' extension requires either 'V' or 'Zve32f' extension");
+  }
+
   if (extension_table[EXT_ZFINX] && extension_table['F']) {
     bad_isa_string(str, ("Zfinx/Zdinx/Zhinx{min} extensions conflict with 'F/D/Q/Zfh{min}' extensions"));
   }

riscv/decode_macros.h

@@ -267,15 +267,21 @@ inline bfloat16_t bf16(freg_t r) { return bf16(unboxBF16(r)); }
 inline float32_t f32(freg_t r) { return f32(unboxF32(r)); }
 inline float64_t f64(freg_t r) { return f64(unboxF64(r)); }
 inline float128_t f128(freg_t r) { return r; }
+inline float16_t f16(freg_t r, reg_t altfmt) { return altfmt ? bf16(r) : f16(r); }
+inline float32_t f32(freg_t r, UNUSED reg_t altfmt) { return f32(r); }
+inline float64_t f64(freg_t r, UNUSED reg_t altfmt) { return f64(r); }
 inline freg_t freg(float16_t f) { return { ((uint64_t)-1 << 16) | f.v, (uint64_t)-1 }; }
 inline freg_t freg(float32_t f) { return { ((uint64_t)-1 << 32) | f.v, (uint64_t)-1 }; }
 inline freg_t freg(float64_t f) { return { f.v, (uint64_t)-1 }; }
 inline freg_t freg(float128_t f) { return f; }
 #define F16_SIGN ((uint16_t)1 << 15)
+#define BF16_SIGN F16_SIGN
 #define F32_SIGN ((uint32_t)1 << 31)
 #define F64_SIGN ((uint64_t)1 << 63)
 #define fsgnj16(a, b, n, x) \
   f16((f16(a).v & ~F16_SIGN) | ((((x) ? f16(a).v : (n) ? F16_SIGN : 0) ^ f16(b).v) & F16_SIGN))
+#define bfsgnj16(a, b, n, x) \
+  bf16((bf16(a).v & ~BF16_SIGN) | ((((x) ? bf16(a).v : (n) ? BF16_SIGN : 0) ^ bf16(b).v) & BF16_SIGN))
 #define fsgnj32(a, b, n, x) \
   f32((f32(a).v & ~F32_SIGN) | ((((x) ? f32(a).v : (n) ? F32_SIGN : 0) ^ f32(b).v) & F32_SIGN))
 #define fsgnj64(a, b, n, x) \

riscv/encoding.h

@@ -4,7 +4,7 @@
 
 /*
  * This file is auto-generated by running 'make' in
- * https://github.com/riscv/riscv-opcodes (a974baa)
+ * https://github.com/riscv/riscv-opcodes (26e2c04)
  */
 
 #ifndef RISCV_CSR_ENCODING_H
@@ -1768,6 +1768,8 @@
 #define MASK_VFMV_S_F 0xfff0707f
 #define MATCH_VFMV_V_F 0x5e005057
 #define MASK_VFMV_V_F 0xfff0707f
+#define MATCH_VFNCVT_F_F_Q 0x480c9057
+#define MASK_VFNCVT_F_F_Q 0xfc0ff07f
 #define MATCH_VFNCVT_F_F_W 0x480a1057
 #define MASK_VFNCVT_F_F_W 0xfc0ff07f
 #define MATCH_VFNCVT_F_X_W 0x48099057
@@ -1780,16 +1782,14 @@
 #define MASK_VFNCVT_RTZ_X_F_W 0xfc0ff07f
 #define MATCH_VFNCVT_RTZ_XU_F_W 0x480b1057
 #define MASK_VFNCVT_RTZ_XU_F_W 0xfc0ff07f
+#define MATCH_VFNCVT_SAT_F_F_Q 0x480d9057
+#define MASK_VFNCVT_SAT_F_F_Q 0xfc0ff07f
 #define MATCH_VFNCVT_X_F_W 0x48089057
 #define MASK_VFNCVT_X_F_W 0xfc0ff07f
 #define MATCH_VFNCVT_XU_F_W 0x48081057
 #define MASK_VFNCVT_XU_F_W 0xfc0ff07f
-#define MATCH_VFNCVTBF16_F_F_Q 0x480c9057
-#define MASK_VFNCVTBF16_F_F_Q 0xfc0ff07f
 #define MATCH_VFNCVTBF16_F_F_W 0x480e9057
 #define MASK_VFNCVTBF16_F_F_W 0xfc0ff07f
-#define MATCH_VFNCVTBF16_SAT_F_F_Q 0x480d9057
-#define MASK_VFNCVTBF16_SAT_F_F_Q 0xfc0ff07f
 #define MATCH_VFNCVTBF16_SAT_F_F_W 0x480f9057
 #define MASK_VFNCVTBF16_SAT_F_F_W 0xfc0ff07f
 #define MATCH_VFNMACC_VF 0xb4005057
@@ -3715,17 +3715,17 @@ DECLARE_INSN(vfmul_vv, MATCH_VFMUL_VV, MASK_VFMUL_VV)
 DECLARE_INSN(vfmv_f_s, MATCH_VFMV_F_S, MASK_VFMV_F_S)
 DECLARE_INSN(vfmv_s_f, MATCH_VFMV_S_F, MASK_VFMV_S_F)
 DECLARE_INSN(vfmv_v_f, MATCH_VFMV_V_F, MASK_VFMV_V_F)
+DECLARE_INSN(vfncvt_f_f_q, MATCH_VFNCVT_F_F_Q, MASK_VFNCVT_F_F_Q)
 DECLARE_INSN(vfncvt_f_f_w, MATCH_VFNCVT_F_F_W, MASK_VFNCVT_F_F_W)
 DECLARE_INSN(vfncvt_f_x_w, MATCH_VFNCVT_F_X_W, MASK_VFNCVT_F_X_W)
 DECLARE_INSN(vfncvt_f_xu_w, MATCH_VFNCVT_F_XU_W, MASK_VFNCVT_F_XU_W)
 DECLARE_INSN(vfncvt_rod_f_f_w, MATCH_VFNCVT_ROD_F_F_W, MASK_VFNCVT_ROD_F_F_W)
 DECLARE_INSN(vfncvt_rtz_x_f_w, MATCH_VFNCVT_RTZ_X_F_W, MASK_VFNCVT_RTZ_X_F_W)
 DECLARE_INSN(vfncvt_rtz_xu_f_w, MATCH_VFNCVT_RTZ_XU_F_W, MASK_VFNCVT_RTZ_XU_F_W)
+DECLARE_INSN(vfncvt_sat_f_f_q, MATCH_VFNCVT_SAT_F_F_Q, MASK_VFNCVT_SAT_F_F_Q)
 DECLARE_INSN(vfncvt_x_f_w, MATCH_VFNCVT_X_F_W, MASK_VFNCVT_X_F_W)
 DECLARE_INSN(vfncvt_xu_f_w, MATCH_VFNCVT_XU_F_W, MASK_VFNCVT_XU_F_W)
-DECLARE_INSN(vfncvtbf16_f_f_q, MATCH_VFNCVTBF16_F_F_Q, MASK_VFNCVTBF16_F_F_Q)
 DECLARE_INSN(vfncvtbf16_f_f_w, MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W)
-DECLARE_INSN(vfncvtbf16_sat_f_f_q, MATCH_VFNCVTBF16_SAT_F_F_Q, MASK_VFNCVTBF16_SAT_F_F_Q)
 DECLARE_INSN(vfncvtbf16_sat_f_f_w, MATCH_VFNCVTBF16_SAT_F_F_W, MASK_VFNCVTBF16_SAT_F_F_W)
 DECLARE_INSN(vfnmacc_vf, MATCH_VFNMACC_VF, MASK_VFNMACC_VF)
 DECLARE_INSN(vfnmacc_vv, MATCH_VFNMACC_VV, MASK_VFNMACC_VV)

riscv/insns/vfadd_vf.h

@@ -1,7 +1,9 @@
 // vfadd.vf vd, vs2, rs1
+require_zvfbfa
+
 VI_VFP_VF_LOOP
 ({
-  vd = f16_add(rs1, vs2);
+  vd = VFP_OP_16(add, vs2, rs1);
 },
 {
   vd = f32_add(rs1, vs2);

riscv/insns/vfadd_vv.h

@@ -1,7 +1,9 @@
 // vfadd.vv vd, vs2, vs1
+require_zvfbfa
+
 VI_VFP_VV_LOOP
 ({
-  vd = f16_add(vs1, vs2);
+  vd = VFP_OP_16(add, vs2, vs1);
 },
 {
   vd = f32_add(vs1, vs2);

riscv/insns/vfclass_v.h

@@ -1,7 +1,7 @@
 // vfclass.v vd, vs2, vm
 VI_VFP_V_LOOP
 ({
-  vd = f16(f16_classify(vs2));
+  vd = P.VU.altfmt ? bf16(bf16_classify(vs2)) : f16(f16_classify(vs2));
 },
 {
   vd = f32(f32_classify(vs2));

riscv/insns/vfdiv_vf.h

@@ -1,4 +1,6 @@
 // vfdiv.vf vd, vs2, rs1
+VI_NON_ALTFMT_INSN
+
 VI_VFP_VF_LOOP
 ({
   vd = f16_div(vs2, rs1);

riscv/insns/vfdiv_vv.h

@@ -1,4 +1,6 @@
 // vfdiv.vv  vd, vs2, vs1
+VI_NON_ALTFMT_INSN
+
 VI_VFP_VV_LOOP
 ({
   vd = f16_div(vs2, vs1);

riscv/insns/vfext_vf2.h

@@ -0,0 +1,14 @@
+static const uint8_t ofp4_to_e4m3[16] = {
+    0x00, 0x30, 0x38, 0x3c, 0x40, 0x44, 0x48, 0x4c,  // positive values (sign bit 0)
+    0x80, 0xb0, 0xb8, 0xbc, 0xc0, 0xc4, 0xc8, 0xcc   // negative values (sign bit 1)
+};
+
+require_extension(EXT_ZVFOFP4MIN);
+VI_NON_ALTFMT_INSN
+VI_VF_EXT(2,
+    {
+        uint_fast8_t packed_ofp4_reg = P.VU.elt<uint8_t>(rs2_num, i / 2);
+        uint_fast8_t data = ((packed_ofp4_reg >> ((i & 1UL)*4)) & 0xF);
+        P.VU.elt<uint8_t>(rd_num, i, true) = ofp4_to_e4m3[data];
+    }
+)