[Zvbc32e] enabling 32-bit vclmul/vclmulh

Author: nibrunie

disasm/disasm.cc

@@ -2184,7 +2184,7 @@ void disassembler_t::add_instructions(const isa_parser_t* isa, bool strict)
 #undef DISASM_VECTOR_VV_VX_VIU_ZIMM6
     }
 
-  if (ext_enabled(EXT_ZVBC)) {
+  if (ext_enabled(EXT_ZVBC) || ext_enabled(EXT_ZVBC32E)) {
 #define DISASM_VECTOR_VV_VX(name) \
     DEFINE_VECTOR_VV(name##_vv); \
     DEFINE_VECTOR_VX(name##_vx)

disasm/isa_parser.cc

@@ -282,6 +282,8 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv)
       extension_table[EXT_ZVBB] = true;
     } else if (ext_str == "zvbc") {
       extension_table[EXT_ZVBC] = true;
+    } else if (ext_str == "zvbc32e") {
+      extension_table[EXT_ZVBC32E] = true;
     } else if (ext_str == "zvfbfmin") {
       extension_table[EXT_ZVFBFMIN] = true;
     } else if (ext_str == "zvfbfwma") {

riscv/decode_macros.h

@@ -163,6 +163,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
 #define require_rv32 require(xlen == 32)
 #define require_extension(s) require(p->extension_enabled(s))
 #define require_either_extension(A,B) require(p->extension_enabled(A) || p->extension_enabled(B));
+#define require_either_extension_condition(A,cA, B, cB) require(p->extension_enabled(A) && (cA) || p->extension_enabled(B) && (cB));
 #define require_impl(s) require(p->supports_impl(s))
 #define require_fp          STATE.fflags->verify_permissions(insn, false)
 #define require_accelerator require(STATE.sstatus->enabled(SSTATUS_XS))

riscv/insns/vclmul_vv.h

@@ -2,13 +2,13 @@
 
 #include "zvk_ext_macros.h"
 
-require_zvbc;
-require(P.VU.vsew == 64);
+require_any_zvbc;
+require_either_extension_condition(EXT_ZVBC, P.VU.vsew == 64, EXT_ZVBC32E, P.VU.vsew == 32);
 
 VI_VV_ULOOP
 ({
-  // Perform a carryless multiplication 64bx64b on each 64b element,
-  // return the low 64b of the 128b product.
+  // Perform a carryless multiplication SEW-bit x SEW-bit on each SEW-bit element,
+  // return the low SEW bits of the (2.SEW)-bit product.
   //   <https://en.wikipedia.org/wiki/Carry-less_product>
   vd = 0;
   for (std::size_t bit_idx = 0; bit_idx < sew; ++bit_idx) {

riscv/insns/vclmul_vx.h

@@ -2,13 +2,13 @@
 
 #include "zvk_ext_macros.h"
 
-require_zvbc;
-require(P.VU.vsew == 64);
+require_any_zvbc;
+require_either_extension_condition(EXT_ZVBC, P.VU.vsew == 64, EXT_ZVBC32E, P.VU.vsew == 32);
 
 VI_VX_ULOOP
 ({
-  // Perform a carryless multiplication 64bx64b on each 64b element,
-  // return the low 64b of the 128b product.
+  // Perform a carryless multiplication SEW-bit x SEW-bit on each SEW-bit element,
+  // return the low SEW bits of the (2.SEW)-bit product.
   //   <https://en.wikipedia.org/wiki/Carry-less_product>
   vd = 0;
   for (std::size_t bit_idx = 0; bit_idx < sew; ++bit_idx) {

riscv/insns/vclmulh_vv.h

@@ -2,8 +2,8 @@
 
 #include "zvk_ext_macros.h"
 
-require_zvbc;
-require(P.VU.vsew == 64);
+require_any_zvbc;
+require_either_extension_condition(EXT_ZVBC, P.VU.vsew == 64, EXT_ZVBC32E, P.VU.vsew == 32);
 
 VI_VV_ULOOP
 ({

riscv/insns/vclmulh_vx.h

@@ -2,13 +2,13 @@
 
 #include "zvk_ext_macros.h"
 
-require_zvbc;
-require(P.VU.vsew == 64);
+require_any_zvbc;
+require_either_extension_condition(EXT_ZVBC, P.VU.vsew == 64, EXT_ZVBC32E, P.VU.vsew == 32);
 
 VI_VX_ULOOP
 ({
-  // Perform a carryless multiplication 64bx64b on each 64b element,
-  // return the high 64b of the 128b product.
+  // Perform a carryless multiplication SEW-bit x SEW-bit on each SEW-bit element,
+  // return the high SEW bits of the (2.SEW)-bit product.
   //   <https://en.wikipedia.org/wiki/Carry-less_product>
   vd = 0;
   for (std::size_t bit_idx = 1; bit_idx < sew; ++bit_idx) {

riscv/isa_parser.h

@@ -60,9 +60,11 @@ typedef enum {
   EXT_ZILSD,
   EXT_ZVBB,
   EXT_ZVBC,
+  EXT_ZVBC32E,
   EXT_ZVFBFMIN,
   EXT_ZVFBFWMA,
   EXT_ZVKG,
+  EXT_ZVKGS,
   EXT_ZVKNED,
   EXT_ZVKNHA,
   EXT_ZVKNHB,

riscv/zvk_ext_macros.h

@@ -29,6 +29,23 @@
     require_extension(EXT_ZVBC); \
   } while (0)
 
+// Ensures that the ZVBC32e extension (vector carryless multiplication
+// with 32-bit elements) is present, and the vector unit is enabled
+// and in a valid state.
+#define require_zvbc32e \
+  do { \
+    require_vector(true); \
+    require_extension(EXT_ZVBC32E); \
+  } while (0)
+
+// Ensures that any ZVBC extensions (vector carryless multiplication)
+// is present, and the vector unit is enabled and in a valid state.
+#define require_any_zvbc \
+  do { \
+    require_vector(true); \
+    require_either_extension(EXT_ZVBC, EXT_ZVBC32E); \
+  } while (0)
+
 // Ensures that the ZVKG extension (vector Galois Field Multiplication)
 // is present, and the vector unit is enabled and in a valid state.
 #define require_zvkg \
@@ -37,6 +54,14 @@
     require_extension(EXT_ZVKG); \
   } while (0)
 
+// Ensures that the ZVKGS extension (vector Galois Field Multiplication
+// with vector-scalar variant) is present, and the vector unit is
+// enabled and in a valid state.
+#define require_zvkgs \
+  do { \
+    require_vector(true); \
+    require_extension(EXT_ZVKGS); \
+  } while (0)
 // Ensures that a ZVK extension supporting SHA-256 is present.
 // For SHA-256, this support is present in either Zvknha or Zvknhb.
 // Also ensures that the vector unit is enabled and in a valid state.