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4 | 4 |
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5 | 5 | /* |
6 | 6 | * This file is auto-generated by running 'make' in |
7 | | - * https://github.com/riscv/riscv-opcodes (c55d30f) |
| 7 | + * https://github.com/riscv/riscv-opcodes (f1d708d) |
8 | 8 | */ |
9 | 9 |
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10 | 10 | #ifndef RISCV_CSR_ENCODING_H |
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110 | 110 | #define DCSR_CAUSE_STEP 4 |
111 | 111 | #define DCSR_CAUSE_HALT 5 |
112 | 112 | #define DCSR_CAUSE_GROUP 6 |
| 113 | +#define DCSR_CAUSE_EXTCAUSE 7 |
| 114 | + |
| 115 | +#define DCSR_EXTCAUSE_CRITERR 0 |
113 | 116 |
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114 | 117 | #define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) |
115 | 118 | #define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) |
116 | 119 | #define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) |
117 | 120 |
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118 | 121 | #define MCONTROL_SELECT (1<<19) |
119 | 122 | #define MCONTROL_TIMING (1<<18) |
120 | | -#define MCONTROL_ACTION (0x3f<<12) |
| 123 | +#define MCONTROL_ACTION (0xf<<12) |
121 | 124 | #define MCONTROL_CHAIN (1<<11) |
122 | 125 | #define MCONTROL_MATCH (0xf<<7) |
123 | 126 | #define MCONTROL_M (1<<6) |
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1840 | 1843 | #define MASK_VFWSUB_WF 0xfc00707f |
1841 | 1844 | #define MATCH_VFWSUB_WV 0xd8001057 |
1842 | 1845 | #define MASK_VFWSUB_WV 0xfc00707f |
| 1846 | +#define MATCH_VGHSH_VS 0x8e002077 |
| 1847 | +#define MASK_VGHSH_VS 0xfe00707f |
1843 | 1848 | #define MATCH_VGHSH_VV 0xb2002077 |
1844 | 1849 | #define MASK_VGHSH_VV 0xfe00707f |
| 1850 | +#define MATCH_VGMUL_VS 0xa608a077 |
| 1851 | +#define MASK_VGMUL_VS 0xfe0ff07f |
1845 | 1852 | #define MATCH_VGMUL_VV 0xa208a077 |
1846 | 1853 | #define MASK_VGMUL_VV 0xfe0ff07f |
1847 | 1854 | #define MATCH_VID_V 0x5008a057 |
@@ -3672,7 +3679,9 @@ DECLARE_INSN(vfwsub_vf, MATCH_VFWSUB_VF, MASK_VFWSUB_VF) |
3672 | 3679 | DECLARE_INSN(vfwsub_vv, MATCH_VFWSUB_VV, MASK_VFWSUB_VV) |
3673 | 3680 | DECLARE_INSN(vfwsub_wf, MATCH_VFWSUB_WF, MASK_VFWSUB_WF) |
3674 | 3681 | DECLARE_INSN(vfwsub_wv, MATCH_VFWSUB_WV, MASK_VFWSUB_WV) |
| 3682 | +DECLARE_INSN(vghsh_vs, MATCH_VGHSH_VS, MASK_VGHSH_VS) |
3675 | 3683 | DECLARE_INSN(vghsh_vv, MATCH_VGHSH_VV, MASK_VGHSH_VV) |
| 3684 | +DECLARE_INSN(vgmul_vs, MATCH_VGMUL_VS, MASK_VGMUL_VS) |
3676 | 3685 | DECLARE_INSN(vgmul_vv, MATCH_VGMUL_VV, MASK_VGMUL_VV) |
3677 | 3686 | DECLARE_INSN(vid_v, MATCH_VID_V, MASK_VID_V) |
3678 | 3687 | DECLARE_INSN(viota_m, MATCH_VIOTA_M, MASK_VIOTA_M) |
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