test

Author: aswaterman

riscv/mmu.h

@@ -291,7 +291,7 @@ class mmu_t
     return have_reservation;
   }
 
-  static const reg_t ICACHE_ENTRIES = 1024;
+  static const reg_t ICACHE_ENTRIES = 8;
 
   inline size_t icache_index(reg_t addr)
   {
@@ -310,22 +310,26 @@ class mmu_t
 
   inline icache_entry_t* refill_icache(reg_t addr, icache_entry_t* entry)
   {
-    insn_bits_t insn = fetch_insn_parcel(addr);
+    insn_bits_t insn;
+    unsigned length;
 
-    int length = insn_length(insn);
+    if (auto [tlb_hit, host_addr, paddr] = access_tlb(tlb_insn, addr);
+        tlb_hit && ((addr % PGSIZE) + sizeof(insn_bits_t) <= PGSIZE)) {
+      insn = from_le(*(insn_parcel_t*)host_addr);
+      length = insn_length(insn);
 
-    if (likely(length == 4)) {
-      insn |= (insn_bits_t)fetch_insn_parcel(addr + 2) << 16;
-    } else if (length == 2) {
-      // entire instruction already fetched
-    } else if (length == 6) {
-      insn |= (insn_bits_t)fetch_insn_parcel(addr + 2) << 16;
-      insn |= (insn_bits_t)fetch_insn_parcel(addr + 4) << 32;
+      for (unsigned pos = sizeof(insn_parcel_t); unlikely(pos < length); pos += sizeof(insn_parcel_t)) {
+        insn |= (insn_bits_t)from_le(*(insn_parcel_t*)(host_addr + pos)) << (8 * pos);
+        length = insn_length(insn);
+      }
     } else {
-      static_assert(sizeof(insn_bits_t) == 8, "insn_bits_t must be uint64_t");
-      insn |= (insn_bits_t)fetch_insn_parcel(addr + 2) << 16;
-      insn |= (insn_bits_t)fetch_insn_parcel(addr + 4) << 32;
-      insn |= (insn_bits_t)fetch_insn_parcel(addr + 6) << 48;
+      insn = fetch_insn_parcel(addr);
+      length = insn_length(insn);
+
+      for (unsigned pos = sizeof(insn_parcel_t); unlikely(pos < length); pos += sizeof(insn_parcel_t)) {
+        insn |= fetch_insn_parcel(addr + pos) << (8 * pos);
+        length = insn_length(insn);
+      }
     }
 
     insn_fetch_t fetch = {proc->decode_insn(insn), insn};