Fix read value of CSR mip.

NewPaulWalker · sinceforYy · NewPaulWalker · commit a5699bf08279 · 2024-12-10T17:09:57.000+08:00
The read value of mip should only depend on the two bits, VSEIP and VSTIP of hvip.

This PR fix the read value of CSR mip when Sscofpmf extension enabled.

After implementing the Sscofpmf extension, hvip.LCOFIP became writable.
This caused an issue where the entire value of hvip was OR-ed when reading mip.

I revise the mip read logic to make it depend only on the hvip.VSEIP and hvip.VSTIP bits.

Co-authored-by: Zhaoyang You &lt;zyyou1998@gmail.com&gt;
diff --git a/riscv/csrs.cc b/riscv/csrs.cc
@@ -781,7 +781,7 @@ mip_csr_t::mip_csr_t(processor_t* const proc, const reg_t addr):
 }
 
 reg_t mip_csr_t::read() const noexcept {
-  return val | state->hvip->basic_csr_t::read();
+  return val | (state->hvip->basic_csr_t::read() & (MIP_VSEIP | MIP_VSTIP));
 }
 
 void mip_csr_t::backdoor_write_with_mask(const reg_t mask, const reg_t val) noexcept {

Original file line number	Diff line number	Diff line change
`@@ -781,7 +781,7 @@ mip_csr_t::mip_csr_t(processor_t* const proc, const reg_t addr):`
`781`	`781`	`}`
`782`	`782`
`783`	`783`	`reg_t mip_csr_t::read() const noexcept {`
`784`		`- return val \| state->hvip->basic_csr_t::read();`
	`784`	`+ return val \| (state->hvip->basic_csr_t::read() & (MIP_VSEIP \| MIP_VSTIP));`
`785`	`785`	`}`
`786`	`786`
`787`	`787`	`void mip_csr_t::backdoor_write_with_mask(const reg_t mask, const reg_t val) noexcept {`