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Merge pull request #2191 from Steven-Li-Xiaogang/master
indirection CSRs 'iprio0~iprio15' are defined by Smaia/Ssaia extensions
2 parents 63c6093 + 6aae741 commit ce747be

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2 files changed

+6
-4
lines changed

2 files changed

+6
-4
lines changed

riscv/csr_init.cc

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ void state_t::add_csr(reg_t addr, const csr_t_p& csr)
1212
#define add_supervisor_csr(addr, csr) add_const_ext_csr('S', addr, csr)
1313
#define add_hypervisor_csr(addr, csr) add_ext_csr('H', addr, csr)
1414

15-
void state_t::add_ireg_proxy(processor_t* const proc, sscsrind_reg_csr_t::sscsrind_reg_csr_t_p ireg)
15+
void state_t::add_iprio_proxy(processor_t* const proc, sscsrind_reg_csr_t::sscsrind_reg_csr_t_p ireg)
1616
{
1717
// This assumes xlen is always max_xlen, which is true today (see
1818
// mstatus_csr_t::unlogged_write()):
@@ -443,7 +443,8 @@ void state_t::csr_init(processor_t* const proc, reg_t max_isa)
443443

444444
sscsrind_reg_csr_t::sscsrind_reg_csr_t_p mireg;
445445
add_csr(CSR_MIREG, mireg = std::make_shared<sscsrind_reg_csr_t>(proc, CSR_MIREG, miselect));
446-
add_ireg_proxy(proc, mireg);
446+
if (proc->extension_enabled_const(EXT_SMAIA))
447+
add_iprio_proxy(proc, mireg);
447448
const reg_t mireg_csrs[] = { CSR_MIREG2, CSR_MIREG3, CSR_MIREG4, CSR_MIREG5, CSR_MIREG6 };
448449
for (auto csr : mireg_csrs)
449450
add_csr(csr, std::make_shared<sscsrind_reg_csr_t>(proc, csr, miselect));
@@ -460,7 +461,8 @@ void state_t::csr_init(processor_t* const proc, reg_t max_isa)
460461
add_hypervisor_csr(CSR_VSIREG, vsireg);
461462

462463
auto sireg = std::make_shared<sscsrind_reg_csr_t>(proc, CSR_SIREG, siselect);
463-
add_ireg_proxy(proc, sireg);
464+
if (proc->extension_enabled_const(EXT_SSAIA))
465+
add_iprio_proxy(proc, sireg);
464466
add_supervisor_csr(CSR_SIREG, std::make_shared<virtualized_indirect_csr_t>(proc, sireg, vsireg));
465467
if (proc->extension_enabled(EXT_SSCCFG) || proc->extension_enabled(EXT_SMCDELEG)) {
466468
// case CSR_SIREG

riscv/processor.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,7 @@ typedef std::vector<std::tuple<reg_t, uint64_t, uint8_t>> commit_log_mem_t;
7777
// architectural state of a RISC-V hart
7878
struct state_t
7979
{
80-
void add_ireg_proxy(processor_t* const proc, sscsrind_reg_csr_t::sscsrind_reg_csr_t_p ireg);
80+
void add_iprio_proxy(processor_t* const proc, sscsrind_reg_csr_t::sscsrind_reg_csr_t_p ireg);
8181
void reset(processor_t* const proc, reg_t max_isa);
8282
void add_csr(reg_t addr, const csr_t_p& csr);
8383

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