@@ -42,7 +42,6 @@ struct insn_fetch_t
4242
4343struct icache_entry_t {
4444 reg_t tag;
45- struct icache_entry_t * next;
4645 insn_fetch_t data;
4746};
4847
@@ -291,7 +290,7 @@ class mmu_t
291290 return have_reservation;
292291 }
293292
294- static const reg_t ICACHE_ENTRIES = 1024 ;
293+ static const reg_t ICACHE_ENTRIES = 4096 ;
295294
296295 inline size_t icache_index (reg_t addr)
297296 {
@@ -311,26 +310,15 @@ class mmu_t
311310 inline icache_entry_t * refill_icache (reg_t addr, icache_entry_t * entry)
312311 {
313312 insn_bits_t insn = fetch_insn_parcel (addr);
313+ unsigned length = insn_length (insn);
314314
315- int length = insn_length (insn);
316-
317- if (likely (length == 4 )) {
318- insn |= (insn_bits_t )fetch_insn_parcel (addr + 2 ) << 16 ;
319- } else if (length == 2 ) {
320- // entire instruction already fetched
321- } else if (length == 6 ) {
322- insn |= (insn_bits_t )fetch_insn_parcel (addr + 2 ) << 16 ;
323- insn |= (insn_bits_t )fetch_insn_parcel (addr + 4 ) << 32 ;
324- } else {
325- static_assert (sizeof (insn_bits_t ) == 8 , " insn_bits_t must be uint64_t" );
326- insn |= (insn_bits_t )fetch_insn_parcel (addr + 2 ) << 16 ;
327- insn |= (insn_bits_t )fetch_insn_parcel (addr + 4 ) << 32 ;
328- insn |= (insn_bits_t )fetch_insn_parcel (addr + 6 ) << 48 ;
315+ for (unsigned pos = sizeof (insn_parcel_t ); pos < length; pos += sizeof (insn_parcel_t )) {
316+ insn |= fetch_insn_parcel (addr + pos) << (8 * pos);
317+ length = insn_length (insn);
329318 }
330319
331320 insn_fetch_t fetch = {proc->decode_insn (insn), insn};
332321 entry->tag = addr;
333- entry->next = &icache[icache_index (addr + length)];
334322 entry->data = fetch;
335323
336324 auto [check_tracer, _, paddr] = access_tlb (tlb_insn, addr, TLB_FLAGS, TLB_CHECK_TRACER);
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