Rename VI_VFP_VV_LOOP_MINI_WIDE to VI_VFP_VV_LOOP_WIDE

Author: rbuchner-aril

riscv/insns/vfwadd_vv.h

@@ -1,5 +1,5 @@
 // vfwadd.vv vd, vs2, vs1
-VI_VFP_VV_LOOP_MINI_WIDE
+VI_VFP_VV_LOOP_WIDE
 ({
   vd = f16_add(vs2, vs1);
 },

riscv/insns/vfwmacc_vv.h

@@ -1,5 +1,5 @@
 // vfwmacc.vv vd, vs2, vs1
-VI_VFP_VV_LOOP_MINI_WIDE
+VI_VFP_VV_LOOP_WIDE
 ({
   vd = f16_mulAdd(vs1, vs2, vd);
 },

riscv/insns/vfwmsac_vv.h

@@ -1,5 +1,5 @@
 // vfwmsac.vv  vd, vs2, vs1
-VI_VFP_VV_LOOP_MINI_WIDE
+VI_VFP_VV_LOOP_WIDE
 ({
   vd = f16_mulAdd(vs1, vs2, f16(vd.v ^ F16_SIGN));
 },

riscv/insns/vfwmul_vv.h

@@ -1,5 +1,5 @@
 // vfwmul.vv vd, vs2, vs1
-VI_VFP_VV_LOOP_MINI_WIDE
+VI_VFP_VV_LOOP_WIDE
 ({
   vd = f16_mul(vs2, vs1);
 },

riscv/insns/vfwnmacc_vv.h

@@ -1,5 +1,5 @@
 // vfwnmacc.vv vd, vs2, vs1
-VI_VFP_VV_LOOP_MINI_WIDE
+VI_VFP_VV_LOOP_WIDE
 ({
   vd = f16_mulAdd(f16(vs1.v ^ F16_SIGN), vs2, f16(vd.v ^ F16_SIGN));
 },

riscv/insns/vfwnmsac_vv.h

@@ -1,5 +1,5 @@
 // vfwnmsac.vv vd, vs2, vs1
-VI_VFP_VV_LOOP_MINI_WIDE
+VI_VFP_VV_LOOP_WIDE
 ({
   vd = f16_mulAdd(f16(vs1.v ^ F16_SIGN), vs2, vd);
 },

riscv/insns/vfwsub_vv.h

@@ -1,5 +1,5 @@
 // vfwsub.vv vd, vs2, vs1
-VI_VFP_VV_LOOP_MINI_WIDE
+VI_VFP_VV_LOOP_WIDE
 ({
   vd = f16_sub(vs2, vs1);
 },

riscv/v_ext_macros.h

@@ -1907,7 +1907,7 @@ reg_t index[P.VU.vlmax]; \
   DEBUG_RVV_FP_VV; \
   VI_VFP_LOOP_END
 
-#define VI_VFP_VV_LOOP_MINI_WIDE(BODY8, BODY16, BODY32)  \
+#define VI_VFP_VV_LOOP_WIDE(BODY8, BODY16, BODY32)  \
   VI_CHECK_DSS(true); \
   VI_VFP_LOOP_BASE \
   switch (P.VU.vsew) { \
@@ -1942,33 +1942,6 @@ reg_t index[P.VU.vlmax]; \
   DEBUG_RVV_FP_VV; \
   VI_VFP_LOOP_END
 
-#define VI_VFP_VV_LOOP_WIDE(BODY16, BODY32) \
-  VI_CHECK_DSS(true); \
-  VI_VFP_LOOP_BASE \
-  switch (P.VU.vsew) { \
-    case e16: { \
-      float32_t &vd = P.VU.elt<float32_t>(rd_num, i, true); \
-      float32_t vs2 = f16_to_f32(P.VU.elt<float16_t>(rs2_num, i)); \
-      float32_t vs1 = f16_to_f32(P.VU.elt<float16_t>(rs1_num, i)); \
-      BODY16; \
-      set_fp_exceptions; \
-      break; \
-    } \
-    case e32: { \
-      float64_t &vd = P.VU.elt<float64_t>(rd_num, i, true); \
-      float64_t vs2 = f32_to_f64(P.VU.elt<float32_t>(rs2_num, i)); \
-      float64_t vs1 = f32_to_f64(P.VU.elt<float32_t>(rs1_num, i)); \
-      BODY32; \
-      set_fp_exceptions; \
-      break; \
-    } \
-    default: \
-      require(0); \
-      break; \
-  }; \
-  DEBUG_RVV_FP_VV; \
-  VI_VFP_LOOP_END
-
 #define VI_VFP_BF16_VV_LOOP_WIDE(BODY) \
   VI_CHECK_DSS(true); \
   VI_VFP_BF16_LOOP_BASE \