[debug] Misc debug fixes

debug/gdbserver.py

@@ -279,7 +279,7 @@ class MemTestReadInvalid(SimpleMemoryTest):
     def test(self):
         bad_address = self.hart.bad_address
         if self.target.support_set_pmp_deny:
-            self.set_pmp_deny(bad_address)
+            self.set_pmp_deny(bad_address, 8)
             self.gdb.command("monitor riscv set_mem_access progbuf abstract")
         good_address = self.hart.ram + 0x80
 
@@ -634,7 +634,7 @@ def early_applicable(self):
         return self.hart.instruction_hardware_breakpoint_count > 0
 
     def test(self):
-        if not self.hart.honors_tdata1_hmode:
+        if not self.hart.honors_tdata1_dmode:
             # Run to main before setting the breakpoint, because startup code
             # will otherwise clear the trigger that we set.
             self.gdb.b("main")
@@ -739,7 +739,7 @@ def set_manual_trigger(self, tdata1, tdata2):
         assert False
 
     def test(self):
-        if not self.hart.honors_tdata1_hmode:
+        if not self.hart.honors_tdata1_dmode:
             # Run to main before setting the breakpoint, because startup code
             # will otherwise clear the trigger that we set.
             self.gdb.b("main")
@@ -758,7 +758,11 @@ def test(self):
                            MCONTROL_TYPE_MATCH)
         tdata1 = set_field(tdata1, MCONTROL_ACTION, MCONTROL_ACTION_DEBUG_MODE)
         tdata1 = set_field(tdata1, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL)
-        tdata1 |= MCONTROL_M | MCONTROL_S | MCONTROL_U | MCONTROL_EXECUTE
+        tdata1 |= MCONTROL_M | MCONTROL_EXECUTE
+        if self.hart.extensionSupported("S"):
+            tdata1 |= MCONTROL_S
+        if self.hart.extensionSupported("U"):
+            tdata1 |= MCONTROL_U
 
         tdata2 = self.gdb.p("&rot13")
 
@@ -1470,7 +1474,7 @@ def test(self):
 
 class TriggerDmode(TriggerTest):
     def early_applicable(self):
-        return self.hart.honors_tdata1_hmode and \
+        return self.hart.honors_tdata1_dmode and \
                 self.hart.instruction_hardware_breakpoint_count > 0
 
     def check_triggers(self, tdata1_lsbs, tdata2):
@@ -1717,7 +1721,8 @@ class TranslateTest(GdbSingleHartTest):
     compile_args = ("programs/translate.c", )
 
     def early_applicable(self):
-        return self.hart.ram_size >= 32 * 1024
+        return self.hart.ram_size >= 32 * 1024 and \
+            self.hart.extensionSupported("S")
 
     def setup(self):
         self.disable_pmp()
@@ -2190,7 +2195,7 @@ def test(self):
         # Use NULL if a known-bad address is not provided.
         bad_address = self.hart.bad_address or 0
         if self.target.support_set_pmp_deny:
-            self.set_pmp_deny(bad_address)
+            self.set_pmp_deny(bad_address, 8)
             self.gdb.command("monitor riscv set_mem_access progbuf abstract")
         self.gdb.p(f"fox=(char*)0x{bad_address:08x}")
         output = self.gdb.c()

debug/targets.py

@@ -23,7 +23,7 @@ class Hart:
     # this value set to False are not compliant with the spec (but still usable
     # as long as running code doesn't try to mess with triggers set by an
     # external debugger).
-    honors_tdata1_hmode = True
+    honors_tdata1_dmode = True
 
     # Address where a r/w/x block of RAM starts, together with its size.
     ram = None

debug/targets/SiFive/Freedom/U500Sim.py

@@ -13,5 +13,5 @@ class U500Sim(targets.Target):
     openocd_config_path = "Freedom.cfg"
     harts = [U500Hart()]
 
-    def target(self):
+    def create(self):
         return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)

debug/testlib.py

@@ -247,7 +247,8 @@ class VcsSim:
     logname = logfile.name
     lognames = [logname]
 
-    def __init__(self, sim_cmd=None, debug=False, timeout=300):
+    def __init__(self, sim_cmd=None, debug=False, timeout=300,
+                 server_started=r"^Listening on port (\d+)$"):
         if sim_cmd:
             cmd = shlex.split(sim_cmd)
         else:
@@ -281,7 +282,7 @@ def __init__(self, sim_cmd=None, debug=False, timeout=300):
                 line = listenfile.readline()
                 if not line:
                     time.sleep(1)
-                match = re.match(r"^Listening on port (\d+)$", line)
+                match = re.match(server_started, line)
                 if match:
                     done = True
                     self.port = int(match.group(1))
@@ -321,11 +322,11 @@ def __init__(self, server_cmd=None, config=None, debug=False, timeout=60,
         # line, since they are executed in order.
         cmd += [
             # Tell OpenOCD to bind gdb to an unused, ephemeral port.
-            "--command", "gdb_port 0",
+            "--command", "gdb port 0",
             # We create a socket for OpenOCD command line (TCL-RPC)
-            "--command", "tcl_port 0",
+            "--command", "tcl port 0",
             # don't use telnet
-            "--command", "telnet_port disabled",
+            "--command", "telnet port disabled",
         ]
 
         if config:
@@ -1137,7 +1138,7 @@ def run_all_tests(module, target, parsed):
         return 0
 
     try:
-        os.makedirs(parsed.logs)
+        os.makedirs(parsed.logs, exist_ok=True)
     except OSError:
         # There's a race where multiple instances of the test program might
         # decide to create the logs directory at the same time.
@@ -1492,14 +1493,16 @@ def set_pmp_deny(self, address, size=4 * 1024):
         self.gdb.p("$pmpcfg0=0x98") # L, NAPOT, !R, !W, !X
         self.gdb.p("$pmpaddr0="
                        f"0x{((address >> 2) | ((size - 1) >> 3)):x}")
-        # PMP changes require an sfence.vma, 0x12000073 is sfence.vma
-        self.gdb.command("monitor riscv exec_progbuf 0x12000073")
+        if self.target.implements_page_virtual_memory:
+            # PMP changes require an sfence.vma, 0x12000073 is sfence.vma
+            self.gdb.command("monitor riscv exec_progbuf 0x12000073")
 
     def reset_pmp_deny(self):
         self.gdb.p("$pmpcfg0=0")
         self.gdb.p("$pmpaddr0=0")
-        # PMP changes require an sfence.vma, 0x12000073 is sfence.vma
-        self.gdb.command("monitor riscv exec_progbuf 0x12000073")
+        if self.target.implements_page_virtual_memory:
+            # PMP changes require an sfence.vma, 0x12000073 is sfence.vma
+            self.gdb.command("monitor riscv exec_progbuf 0x12000073")
 
     def disable_pmp(self):
         # Disable physical memory protection by allowing U mode access to all