task: fix typos (#624)

relates to #623

Author: kbroch-rivosinc

arch/isa/globals.isa

@@ -2844,7 +2844,7 @@ function amo {
   returns Bits<N>
   arguments
     XReg virtual_address,  # the virtual address to load from/store to
-    Bits<N> value,         # the value for the second hald of the atomic operation
+    Bits<N> value,         # the value for the second half of the atomic operation
     AmoOperation op,       # atomic operation to apply
     Bits<1>    aq,         # acquire semantics? 0=no, 1=yes
     Bits<1>    rl,         # release semantics? 0=no, 1=yes

arch/profile/RVB23U64.yaml

@@ -39,7 +39,7 @@ extensions:
     presence: mandatory
     version: "~>1.0"
     note: |
-      Commpressed (16-bit) may-be operations
+      Compressed (16-bit) may-be operations
   Zcb:
     presence: mandatory
     version: "~>1.0"

backends/certificate_doc/templates/certificate.adoc.erb

@@ -71,10 +71,10 @@ with the RVI TSC (Technical Steering Committee) organization who creates RISC-V
 
 The CRDs refer to and augment information provided in existing ratified RVI standards.
 
-There are a variety of certificates offered by RVI to accomodate the various RVI standards.
+There are a variety of certificates offered by RVI to accommodate the various RVI standards.
 There are certificates for processors, non-processor system IP (e.g., IOMMU),
 and system platforms (processor + system IP) hardware standards.
-There are multiple classes of processor certificates available to accomodate the wide range of
+There are multiple classes of processor certificates available to accommodate the wide range of
 RISC-V implementations from basic microcontrollers to advanced Applications-class processors.
 
 Each CRD has a list of mandatory behaviors along with a list of optional behaviors.
@@ -152,7 +152,7 @@ Where:
 * <model> is 3-digit integer defined as follows:
 ** The hundreds's digit indicates the series
 ** The ten's digit identifies large differences in mandatory extensions (e.g., V, H) within the series
-** The one's digit indentifies small/medium differences in mandatory extensions (e.g., Zicond, PMP) within the series
+** The one's digit identifies small/medium differences in mandatory extensions (e.g., Zicond, PMP) within the series
 * <base> is optional and is 32 for RV32I, 64 for RV64I, and 32E for RV32E
 ** If a CRD supports multiple bases and <base> is omitted in a reference, it applies to all supported bases
 ** If a CRD only supports one base then <base> is generally omitted

backends/cpp_hart_gen/cpp/include/udb/bits.hpp

@@ -258,7 +258,7 @@ namespace udb {
         // exactly fits in a native type, so just cast it
         return static_cast<SignedStorageType>(unsigned_value);
       } else {
-        // we have a native type, but some bits are unsed. need to sign extend
+        // we have a native type, but some bits are unused. need to sign extend
         // the storage to the native width
         return static_cast<SignedStorageType>(sign_extend(unsigned_value));
       }

backends/cpp_hart_gen/cpp/include/udb/csr.hpp

@@ -41,7 +41,7 @@ namespace udb {
                           const unsigned& xlen) = 0;
 
     // write the field, applying any restrictions first
-    // given teh effective xlen
+    // given the effective xlen
     // virtual void sw_write(const uint64_t& field_write_value,
     //                       const unsigned& xlen) = 0;
 
@@ -113,7 +113,7 @@ namespace udb {
     // no checks or transformations are applied
     virtual void hw_write(const uint64_t& value, const unsigned& xlen) = 0;
 
-    // cant this CSR be implemented when ext is not?
+    // can't this CSR be implemented when ext is not?
     virtual bool implemented_without_Q_(const ExtensionName&) const = 0;
   };
 }  // namespace udb

backends/cpp_hart_gen/cpp/include/udb/defines.hpp

@@ -6,7 +6,7 @@
 #include <version>
 
 // type to be used when you want to pass a string literal as a template
-// arugment
+// argument
 template <size_t N = 0>
 struct TemplateString {
   constexpr TemplateString(const char (&str)[N]) : size(N) {

backends/cpp_hart_gen/cpp/include/udb/version.hpp

@@ -145,7 +145,7 @@ namespace udb {
       OpKind m_kind;
     };
 
-    // default requiremnt is >= 0
+    // default requirement is >= 0
     VersionRequirement() : m_op(OpKind::GTE), m_version(0, 0, 0, false) {}
 
     constexpr VersionRequirement(const std::string_view& req)

backends/cpp_hart_gen/cpp/src/libhart_renode.cpp

@@ -24,7 +24,7 @@ struct RenodeSocModel {
   uint64_t read_mcycle() { return 0; }
   uint64_t read_mtime() { return 0; }
 
-  // returns new value of mcycle (coudl be different than new_value)
+  // returns new value of mcycle (could be different than new_value)
   uint64_t sw_write_mcycle(uint64_t new_value) { return 0; }
 
   void cache_block_zero(uint64_t paddr) {}

backends/cpp_hart_gen/cpp/test/test_bits.cpp

@@ -115,22 +115,22 @@ TEST_CASE("Inversion", "[bits]") {
   REQUIRE((~Bits<129>(5)).get() == 0x1fffffffffffffffffffffffffffffffa_mpz);
   REQUIRE((~Bits<129>(5)).get<int64_t>() < 0);
 }
-TEST_CASE("64-bit Assignement", "[bits]") {
+TEST_CASE("64-bit Assignment", "[bits]") {
   Bits<64> a{5};
   Bits<64> b;
   b = a;
   REQUIRE(a.get() == b.get());
   REQUIRE(a.get() == 5);
 }
-TEST_CASE("65-bit Assignement", "[bits]") {
+TEST_CASE("65-bit Assignment", "[bits]") {
   Bits<65> a{5};
   Bits<65> b;
   b = a;
   REQUIRE(a.get() == b.get());
   REQUIRE(a.get() == 5);
 }
 
-TEST_CASE("129-bit Assignement", "[bits]") {
+TEST_CASE("129-bit Assignment", "[bits]") {
   Bits<129> a{5};
   Bits<129> b;
   b = a;

backends/cpp_hart_gen/cpp/test/test_version.cpp

@@ -47,7 +47,7 @@ TEST_CASE("version ordering", "[version]") {
   REQUIRE(v2 >= v1);
 }
 
-TEST_CASE("version ordering iwth pre", "[version]") {
+TEST_CASE("version ordering with pre", "[version]") {
   Version v1("2.1.3-pre"sv);
   Version v2("2.1.3"sv);