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Xqciv0p7 (#475)
* Xqci extension: fixing typo in qc.c.delay instruction name Signed-off-by: Albert Yosher <[email protected]> * Xqci extension: Fixing addresses of qc_mclicie* CSRs Signed-off-by: Albert Yosher <[email protected]> * Xqci extension: Fix version history of Xqciac sub-extension Signed-off-by: Albert Yosher <[email protected]> * Xqci/Xqccmp extensions, qc_iu configuration: update configuration to include correct extensions Signed-off-by: Albert Yosher <[email protected]> * Xqci: rename custom CSRs to use 'qc.' prefix instead of 'qc_' prefix Signed-off-by: Albert Yosher <[email protected]> * Xqci extension: update Xqcibm instrctions to change how bitfield width is taken Signed-off-by: Albert Yosher <[email protected]> * Xqci extension: rename CSRs of Xqciint sub-extension to use dot separator instead underscore Signed-off-by: Albert Yosher <[email protected]> * Xqci extension: add custom CSRs qc.mntvec, qc.mscratch0, qc.mscratch1, qc.mthreadptr; add custom fields to CSR mcause Signed-off-by: Albert Yosher <[email protected]> * Xqci extension: add missing custom CSR registers of Xqciint, add supported exceptions Signed-off-by: Albert Yosher <[email protected]> * Xqci extension: fix typo for PDF document generation in IDL code for few instructions Signed-off-by: Albert Yosher <[email protected]> * Xqci extension: in Xqcia sub-spec fix typo in description of qc.shlsat and qc.shlusat instructions Signed-off-by: Albert Yosher <[email protected]> * Xqci/Xqccmp extensions: resolve conflicts on duplication of exception codes and CSR registers, update version dependency of CSR rgisters Signed-off-by: Albert Yosher <[email protected]> * Xqci/Xqciint extension: adjust descriptions, instructions, CSR and SDL logic to use Smrnmi/Smdbltrp Signed-off-by: Albert Yosher <[email protected]> * Xqci/Xqcibm extension: fix IDL code of qc.cto instruction Signed-off-by: Albert Yosher <[email protected]> * Xqci extension / qc_iu condifuration update to include Smrnmi and Smdbltrp Signed-off-by: Albert Yosher <[email protected]> * Xqci/Xqciint extension: make PDF doc building again Signed-off-by: Albert Yosher <[email protected]> * Xqci/Xqciint extension: fix IDL code of interrupt-related instructions to use custom CSR qc.mcause Signed-off-by: Albert Yosher <[email protected]> * Xqci extension: additional fix to qc.cto instruction IDL code Signed-off-by: Albert Yosher <[email protected]> * Xqci/Xqciint extension: fix qc.c.mienter.nest, should use only qc.mcause CSR Signed-off-by: Albert Yosher <[email protected]> * Xqci/Xqcia extension: porting AntonJohansson IDL code fixes for bugs with saturation instructions qc.addsat, qc.addusat, qc.subsat (clobering saturation results) and qc.shlsat fix (incorrect ILD code logic) Signed-off-by: Albert Yosher <[email protected]> --------- Signed-off-by: Albert Yosher <[email protected]> Signed-off-by: Albert Yosher <[email protected]>
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‎cfgs/qc_iu/arch_overlay/csr/Xqci/gen_mcliciX.rb‎

Lines changed: 139 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -4,55 +4,158 @@
44
pend_template = <<~YAML
55
# yaml-language-server: $schema=../../../../../schemas/csr_schema.json
66
7-
qc_mclicip<%= num %>:
8-
long_name: IRQ Pending <%= num %>
9-
address: 0x<%= (0x7f0 + num).to_s(16) %>
10-
length: 32
11-
priv_mode: M
12-
base: 32
13-
definedBy: Xqci
14-
description: |
15-
Pending bits for IRQs <%= num*32 %>-<%= (num + 1)*32 - 1 %>
16-
fields:
17-
<%- 32.times do |i| -%>
18-
IRQ<%= num*32 + i %>:
19-
type: RW
20-
reset_value: 0
21-
location: <%= i %>
22-
description: IRQ<%= num*32 + i %> pending
23-
<%- end -%>
7+
kind: csr
8+
name: qc.mclicip<%= num %>
9+
long_name: IRQ Pending <%= num %>
10+
address: 0x<%= (0x7f0 + num).to_s(16) %>
11+
length: 32
12+
priv_mode: M
13+
base: 32
14+
definedBy:
15+
anyOf:
16+
- Xqci
17+
- Xqciint
18+
description: |
19+
Pending bits for IRQs <%= num*32 %>-<%= (num + 1)*32 - 1 %>
20+
fields:
21+
<%- 32.times do |i| -%>
22+
IRQ<%= num*32 + i %>:
23+
type: RW
24+
reset_value: 0
25+
location: <%= i %>
26+
description: IRQ<%= num*32 + i %> pending
27+
<%- end -%>
2428
YAML
2529

2630
en_template = <<~YAML
2731
# yaml-language-server: $schema=../../../../../schemas/csr_schema.json
2832
29-
qc_mclicie<%= num %>:
30-
long_name: IRQ Enable <%= num %>
31-
address: 0x<%= (0x7f0 + num).to_s(16) %>
32-
length: 32
33-
base: 32
34-
priv_mode: M
35-
definedBy: Xqci
36-
description: |
37-
Enable bits for IRQs <%= num*32 %>-<%= (num + 1)*32 - 1 %>
38-
fields:
39-
<%- 32.times do |i| -%>
40-
IRQ<%= num*32 + i %>:
41-
type: RW
42-
reset_value: 0
43-
location: <%= i %>
44-
description: IRQ<%= num*32 + i %> enabled
45-
<%- end -%>
33+
kind: csr
34+
name: qc.mclicie<%= num %>
35+
long_name: IRQ Enable <%= num %>
36+
address: 0x<%= (0x7f8 + num).to_s(16) %>
37+
length: 32
38+
base: 32
39+
priv_mode: M
40+
definedBy:
41+
anyOf:
42+
- Xqci
43+
- Xqciint
44+
description: |
45+
Enable bits for IRQs <%= num*32 %>-<%= (num + 1)*32 - 1 %>
46+
fields:
47+
<%- 32.times do |i| -%>
48+
IRQ<%= num*32 + i %>:
49+
type: RW
50+
reset_value: 0
51+
location: <%= i %>
52+
description: IRQ<%= num*32 + i %> enabled
53+
<%- end -%>
54+
YAML
55+
56+
level_template = <<~YAML
57+
# yaml-language-server: $schema=../../../../../schemas/csr_schema.json
58+
59+
kind: csr
60+
name: qc.mclicilvl<%= num.to_s.rjust(2, "0") %>
61+
long_name: IRQ Level <%= num %>
62+
address: 0x<%= (0xbc0 + num).to_s(16) %>
63+
length: 32
64+
priv_mode: M
65+
base: 32
66+
definedBy:
67+
anyOf:
68+
- name: Xqci
69+
version: ">=0.7"
70+
- name: Xqciint
71+
version: ">=0.4"
72+
description: |
73+
Level bits for IRQs <%= num*8 %>-<%= (num + 1)*8 - 1 %>
74+
fields:
75+
<%- 8.times do |i| -%>
76+
IRQ<%= num*8 + i %>:
77+
type: RW
78+
reset_value: 0
79+
location: <%= i * 4 + 3 %> - <%= i * 4 %>
80+
description: IRQ<%= num*8 + i %> level
81+
<%- end -%>
82+
YAML
83+
84+
wp_start_template = <<~YAML
85+
# yaml-language-server: $schema=../../../../../schemas/csr_schema.json
86+
87+
kind: csr
88+
name: qc.mwpstartaddr<%= num %>
89+
long_name: Watchpoint start address for region <%= num %>
90+
address: 0x<%= (0x7d0 + num).to_s(16) %>
91+
length: 32
92+
priv_mode: M
93+
base: 32
94+
definedBy:
95+
anyOf:
96+
- name: Xqci
97+
version: ">=0.7"
98+
- name: Xqciint
99+
version: ">=0.4"
100+
description: |
101+
Watchpoint start address for region <%= num %>
102+
fields:
103+
ADDR:
104+
type: RW
105+
reset_value: 0
106+
location: 31-0
107+
description: Watchpoint start address
108+
YAML
109+
110+
wp_end_template = <<~YAML
111+
# yaml-language-server: $schema=../../../../../schemas/csr_schema.json
112+
113+
kind: csr
114+
name: qc.mwpendaddr<%= num %>
115+
long_name: Watchpoint end address for region <%= num %>
116+
address: 0x<%= (0x7d4 + num).to_s(16) %>
117+
length: 32
118+
priv_mode: M
119+
base: 32
120+
definedBy:
121+
anyOf:
122+
- name: Xqci
123+
version: ">=0.7"
124+
- name: Xqciint
125+
version: ">=0.4"
126+
description: |
127+
Watchpoint end address for region <%= num %>
128+
fields:
129+
ADDR:
130+
type: RW
131+
reset_value: 0
132+
location: 31-0
133+
description: Watchpoint end address
46134
YAML
47135

48136
root = File.dirname(__FILE__)
49137

50138
erb = ERB.new(pend_template, trim_mode: '-')
51139
8.times do |num|
52-
File.write("#{root}/qc_mclicip#{num}.yaml", erb.result(binding))
140+
File.write("#{root}/qc.mclicip#{num}.yaml", erb.result(binding))
53141
end
54142

55143
erb = ERB.new(en_template, trim_mode: '-')
56144
8.times do |num|
57-
File.write("#{root}/qc_mclicie#{num}.yaml", erb.result(binding))
145+
File.write("#{root}/qc.mclicie#{num}.yaml", erb.result(binding))
146+
end
147+
148+
erb = ERB.new(level_template, trim_mode: '-')
149+
32.times do |num|
150+
File.write("#{root}/qc.mclicilvl#{num.to_s.rjust(2, "0")}.yaml", erb.result(binding))
151+
end
152+
153+
erb = ERB.new(wp_start_template, trim_mode: '-')
154+
4.times do |num|
155+
File.write("#{root}/qc.mwpstartaddr#{num}.yaml", erb.result(binding))
156+
end
157+
158+
erb = ERB.new(wp_end_template, trim_mode: '-')
159+
4.times do |num|
160+
File.write("#{root}/qc.mwpendaddr#{num}.yaml", erb.result(binding))
58161
end

‎cfgs/qc_iu/arch_overlay/csr/Xqci/qc.mcause.yaml‎

Lines changed: 79 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,79 @@
1+
# yaml-language-server: $schema=../../../../../schemas/csr_schema.json
2+
3+
$schema: csr_schema.json#
4+
kind: csr
5+
name: qc.mcause
6+
long_name: Machine Mode Custom Cause Register
7+
address: 0x7c9
8+
base: 32
9+
priv_mode: M
10+
length: MXLEN
11+
description: |
12+
Machine Mode Custom Cause Register / Interrupt context register.
13+
definedBy:
14+
anyOf:
15+
- name: Xqci
16+
version: ">=0.7"
17+
- name: Xqciint
18+
version: ">=0.4"
19+
fields:
20+
INT:
21+
location: 31
22+
description: Alias of mcause.INT bit, if 1'b1 - interrupt processing, if 1'b0 - exception processing.
23+
type: RW-H
24+
reset_value: 0
25+
NMIE:
26+
location: 30
27+
description: Alias of mnstatus.NMIE, if 1'b0, currently processing NMI or double trap.
28+
type: RW-H
29+
reset_value: 0
30+
MPDT:
31+
location: 29
32+
description: M-mode Previous Disable Trap, value of mstatush.MDT at the moment of interrupt/exception.
33+
type: RW-H
34+
reset_value: 0
35+
MNPIE:
36+
type: RW-H
37+
reset_value: 0
38+
location: 28
39+
description: M-mode NMI Previous Interrupt Enable, value of mstatus.MIE at the moment of NMI/double trap.
40+
MPIE:
41+
type: RW-H
42+
reset_value: 0
43+
location: 27
44+
description: Alias of mstatus.MPIE, M-mode Previous Interrupt Enable.
45+
MIE:
46+
type: RW-H
47+
reset_value: 0
48+
location: 26
49+
description: Alias of mstatus.MIE, M-mode Interrupt Enable.
50+
EXCP:
51+
type: RW-H
52+
reset_value: 0
53+
location: 25
54+
description: Exception Pending Bit, cleaned when exception acknowledged.
55+
NMIP:
56+
type: RW-H
57+
reset_value: 0
58+
location: 24
59+
description: NMI Pending Bit, cleaned when NMI acknowledged.
60+
MNPIL:
61+
type: RW-H
62+
reset_value: 0
63+
location: 23-20
64+
description: M-mode NMI Previous Interrupt Level, value of qc.mcause.MIL at the moment of NMI/double trap.
65+
MPIL:
66+
type: RW-H
67+
reset_value: 0
68+
location: 19-16
69+
description: M-mode Previous Interrupt Level, value of qc.mcause.MIL at the moment of interrupt/exception.
70+
MIL:
71+
type: RW-H
72+
reset_value: 15
73+
location: 15-12
74+
description: M-mode Interrupt Level.
75+
EXCCODE:
76+
type: RW-H
77+
reset_value: 0
78+
location: 11-0
79+
description: Alias of mcause.EXCCODE[11:0], Interrupt/Exception code ID.

‎cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie0.yaml‎ renamed to ‎cfgs/qc_iu/arch_overlay/csr/Xqci/qc.mclicie0.yaml‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,9 @@
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# yaml-language-server: $schema=../../../../../schemas/csr_schema.json
22

3-
$schema: csr_schema.json#
43
kind: csr
5-
name: qc_mclicie0
4+
name: qc.mclicie0
65
long_name: IRQ Enable 0
7-
address: 0x7f0
6+
address: 0x7f8
87
length: 32
98
base: 32
109
priv_mode: M

‎cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie1.yaml‎ renamed to ‎cfgs/qc_iu/arch_overlay/csr/Xqci/qc.mclicie1.yaml‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,9 @@
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# yaml-language-server: $schema=../../../../../schemas/csr_schema.json
22

3-
$schema: csr_schema.json#
43
kind: csr
5-
name: qc_mclicie1
4+
name: qc.mclicie1
65
long_name: IRQ Enable 1
7-
address: 0x7f1
6+
address: 0x7f9
87
length: 32
98
base: 32
109
priv_mode: M

‎cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie2.yaml‎ renamed to ‎cfgs/qc_iu/arch_overlay/csr/Xqci/qc.mclicie2.yaml‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,9 @@
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# yaml-language-server: $schema=../../../../../schemas/csr_schema.json
22

3-
$schema: csr_schema.json#
43
kind: csr
5-
name: qc_mclicie2
4+
name: qc.mclicie2
65
long_name: IRQ Enable 2
7-
address: 0x7f2
6+
address: 0x7fa
87
length: 32
98
base: 32
109
priv_mode: M

‎cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie3.yaml‎ renamed to ‎cfgs/qc_iu/arch_overlay/csr/Xqci/qc.mclicie3.yaml‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,9 @@
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# yaml-language-server: $schema=../../../../../schemas/csr_schema.json
22

3-
$schema: csr_schema.json#
43
kind: csr
5-
name: qc_mclicie3
4+
name: qc.mclicie3
65
long_name: IRQ Enable 3
7-
address: 0x7f3
6+
address: 0x7fb
87
length: 32
98
base: 32
109
priv_mode: M

‎cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie4.yaml‎ renamed to ‎cfgs/qc_iu/arch_overlay/csr/Xqci/qc.mclicie4.yaml‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,9 @@
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# yaml-language-server: $schema=../../../../../schemas/csr_schema.json
22

3-
$schema: csr_schema.json#
43
kind: csr
5-
name: qc_mclicie4
4+
name: qc.mclicie4
65
long_name: IRQ Enable 4
7-
address: 0x7f4
6+
address: 0x7fc
87
length: 32
98
base: 32
109
priv_mode: M

‎cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie5.yaml‎ renamed to ‎cfgs/qc_iu/arch_overlay/csr/Xqci/qc.mclicie5.yaml‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,9 @@
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# yaml-language-server: $schema=../../../../../schemas/csr_schema.json
22

3-
$schema: csr_schema.json#
43
kind: csr
5-
name: qc_mclicie5
4+
name: qc.mclicie5
65
long_name: IRQ Enable 5
7-
address: 0x7f5
6+
address: 0x7fd
87
length: 32
98
base: 32
109
priv_mode: M

‎cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie6.yaml‎ renamed to ‎cfgs/qc_iu/arch_overlay/csr/Xqci/qc.mclicie6.yaml‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,9 @@
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# yaml-language-server: $schema=../../../../../schemas/csr_schema.json
22

3-
$schema: csr_schema.json#
43
kind: csr
5-
name: qc_mclicie6
4+
name: qc.mclicie6
65
long_name: IRQ Enable 6
7-
address: 0x7f6
6+
address: 0x7fe
87
length: 32
98
base: 32
109
priv_mode: M

‎cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie7.yaml‎ renamed to ‎cfgs/qc_iu/arch_overlay/csr/Xqci/qc.mclicie7.yaml‎

Lines changed: 2 additions & 3 deletions
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@@ -1,10 +1,9 @@
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# yaml-language-server: $schema=../../../../../schemas/csr_schema.json
22

3-
$schema: csr_schema.json#
43
kind: csr
5-
name: qc_mclicie7
4+
name: qc.mclicie7
65
long_name: IRQ Enable 7
7-
address: 0x7f7
6+
address: 0x7ff
87
length: 32
98
base: 32
109
priv_mode: M

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