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fix(data): floating-point loads/stores several issues (#806)
- make sure the loads load to a float register - make sure the stores store from a float register - update the corresponding field names, description, IDL - make sure the assembly syntax are correct - add a few missing "long_name" - remove an extraneous `$`
1 parent 9271409 commit 612c0ac

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8 files changed

+35
-35
lines changed

8 files changed

+35
-35
lines changed

‎arch/inst/D/fld.yaml‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3,19 +3,19 @@
33
$schema: inst_schema.json#
44
kind: instruction
55
name: fld
6-
long_name: No synopsis available
6+
long_name: Load Double-precision Floating-Point
77
description: |
88
No description available.
99
definedBy: D
10-
assembly: xd, xs1, imm
10+
assembly: fd, xs1, imm
1111
encoding:
1212
match: -----------------011-----0000111
1313
variables:
1414
- name: imm
1515
location: 31-20
16-
- name: rs1
16+
- name: xs1
1717
location: 19-15
18-
- name: rd
18+
- name: fd
1919
location: 11-7
2020
access:
2121
s: always

‎arch/inst/D/fsd.yaml‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7,15 +7,15 @@ long_name: No synopsis available
77
description: |
88
No description available.
99
definedBy: D
10-
assembly: xs1, xs2, imm
10+
assembly: fs2, imm(xs1)
1111
encoding:
1212
match: -----------------011-----0100111
1313
variables:
1414
- name: imm
1515
location: 31-25|11-7
16-
- name: rs2
16+
- name: fs2
1717
location: 24-20
18-
- name: rs1
18+
- name: xs1
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location: 19-15
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access:
2121
s: always

‎arch/inst/F/flw.yaml‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ kind: instruction
55
name: flw
66
long_name: Single-precision floating-point load
77
description: |
8-
The `flw` instruction loads a single-precision floating-point value from memory at address _rs1_ + _imm_ into floating-point register _fd_.
8+
The `flw` instruction loads a single-precision floating-point value from memory at address _xs1_ + _imm_ into floating-point register _fd_.
99
1010
`flw` does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.
1111
@@ -16,7 +16,7 @@ encoding:
1616
variables:
1717
- name: imm
1818
location: 31-20
19-
- name: rs1
19+
- name: xs1
2020
location: 19-15
2121
- name: fd
2222
location: 11-7
@@ -29,7 +29,7 @@ data_independent_timing: true
2929
operation(): |
3030
check_f_ok($encoding);
3131
32-
XReg virtual_address = X[rs1] + $signed(imm);
32+
XReg virtual_address = X[xs1] + $signed(imm);
3333
3434
Bits<32> sp_value = read_memory<32>(virtual_address, $encoding);
3535

‎arch/inst/F/fsw.yaml‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ kind: instruction
55
name: fsw
66
long_name: Single-precision floating-point store
77
description: |
8-
The `fsw` instruction stores a single-precision floating-point value in _fs2_ to memory at address _rs1_ + _imm_.
8+
The `fsw` instruction stores a single-precision floating-point value in _fs2_ to memory at address _xs1_ + _imm_.
99
1010
`fsw` does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.
1111
@@ -18,7 +18,7 @@ encoding:
1818
location: 31-25|11-7
1919
- name: fs2
2020
location: 24-20
21-
- name: rs1
21+
- name: xs1
2222
location: 19-15
2323
access:
2424
s: always
@@ -29,7 +29,7 @@ data_independent_timing: true
2929
operation(): |
3030
check_f_ok($encoding);
3131
32-
XReg virtual_address = X[rs1] + $signed(imm);
32+
XReg virtual_address = X[xs1] + $signed(imm);
3333
3434
write_memory<32>(virtual_address, f[fs2][31:0], $encoding);
3535

‎arch/inst/Q/flq.yaml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ encoding:
1313
variables:
1414
- name: imm
1515
location: 31-20
16-
- name: rs1
16+
- name: xs1
1717
location: 19-15
1818
- name: qd
1919
location: 11-7

‎arch/inst/Q/fsq.yaml‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,15 +7,15 @@ long_name: No synopsis available
77
description: |
88
No description available.
99
definedBy: Q
10-
assembly: xs1, qs2, imm
10+
assembly: qs2, imm(xs1)
1111
encoding:
1212
match: -----------------100-----0100111
1313
variables:
1414
- name: imm
1515
location: 31-25|11-7
1616
- name: qs2
1717
location: 24-20
18-
- name: rs1
18+
- name: xs1
1919
location: 19-15
2020
access:
2121
s: always

‎arch/inst/Zfh/flh.yaml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ kind: instruction
55
name: flh
66
long_name: Half-precision floating-point load
77
description: |
8-
The `flh` instruction loads a single-precision floating-point value from memory at address _rs1_ + _imm_ into floating-point register _rd_.
8+
The `flh` instruction loads a single-precision floating-point value from memory at address _xs1_ + _imm_ into floating-point register _rd_.
99
1010
`flh` does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.
1111

‎backends/instructions_appendix/all_instructions.golden.adoc‎

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -9247,12 +9247,12 @@ Included in::
92479247
== fld
92489248

92499249
Synopsis::
9250-
No synopsis available
9250+
Load Double-precision Floating-Point
92519251

92529252
Encoding::
92539253
[wavedrom, ,svg,subs='attributes',width="100%"]
92549254
....
9255-
{"reg":[{"bits":7,"name": 0x7,"type":2},{"bits":5,"name": "rd","type":4},{"bits":3,"name": 0x3,"type":2},{"bits":5,"name": "rs1","type":4},{"bits":12,"name": "imm","type":4}]}
9255+
{"reg":[{"bits":7,"name": 0x7,"type":2},{"bits":5,"name": "fd","type":4},{"bits":3,"name": 0x3,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":12,"name": "imm","type":4}]}
92569256
....
92579257

92589258
Description::
@@ -9264,8 +9264,8 @@ Decode Variables::
92649264
|===
92659265
|Variable Name |Location
92669266
|imm |$encoding[31:20]
9267-
|rs1 |$encoding[19:15]
9268-
|rd |$encoding[11:7]
9267+
|xs1 |$encoding[19:15]
9268+
|fd |$encoding[11:7]
92699269
|===
92709270

92719271
Included in::
@@ -9582,7 +9582,7 @@ Encoding::
95829582
....
95839583

95849584
Description::
9585-
The xref:insts:flh.adoc#udb:doc:inst:flh[flh] instruction loads a single-precision floating-point value from memory at address _rs1_ + _imm_ into floating-point register _rd_.
9585+
The xref:insts:flh.adoc#udb:doc:inst:flh[flh] instruction loads a single-precision floating-point value from memory at address _xs1_ + _imm_ into floating-point register _rd_.
95869586

95879587
xref:insts:flh.adoc#udb:doc:inst:flh[flh] does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.
95889588

@@ -9763,7 +9763,7 @@ No synopsis available
97639763
Encoding::
97649764
[wavedrom, ,svg,subs='attributes',width="100%"]
97659765
....
9766-
{"reg":[{"bits":7,"name": 0x7,"type":2},{"bits":5,"name": "qd","type":4},{"bits":3,"name": 0x4,"type":2},{"bits":5,"name": "rs1","type":4},{"bits":12,"name": "imm","type":4}]}
9766+
{"reg":[{"bits":7,"name": 0x7,"type":2},{"bits":5,"name": "qd","type":4},{"bits":3,"name": 0x4,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":12,"name": "imm","type":4}]}
97679767
....
97689768

97699769
Description::
@@ -9775,7 +9775,7 @@ Decode Variables::
97759775
|===
97769776
|Variable Name |Location
97779777
|imm |$encoding[31:20]
9778-
|rs1 |$encoding[19:15]
9778+
|xs1 |$encoding[19:15]
97799779
|qd |$encoding[11:7]
97809780
|===
97819781

@@ -10087,11 +10087,11 @@ Single-precision floating-point load
1008710087
Encoding::
1008810088
[wavedrom, ,svg,subs='attributes',width="100%"]
1008910089
....
10090-
{"reg":[{"bits":7,"name": 0x7,"type":2},{"bits":5,"name": "fd","type":4},{"bits":3,"name": 0x2,"type":2},{"bits":5,"name": "rs1","type":4},{"bits":12,"name": "imm","type":4}]}
10090+
{"reg":[{"bits":7,"name": 0x7,"type":2},{"bits":5,"name": "fd","type":4},{"bits":3,"name": 0x2,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":12,"name": "imm","type":4}]}
1009110091
....
1009210092

1009310093
Description::
10094-
The xref:insts:flw.adoc#udb:doc:inst:flw[flw] instruction loads a single-precision floating-point value from memory at address _rs1_ + _imm_ into floating-point register _fd_.
10094+
The xref:insts:flw.adoc#udb:doc:inst:flw[flw] instruction loads a single-precision floating-point value from memory at address _xs1_ + _imm_ into floating-point register _fd_.
1009510095

1009610096
xref:insts:flw.adoc#udb:doc:inst:flw[flw] does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.
1009710097

@@ -10101,7 +10101,7 @@ Decode Variables::
1010110101
|===
1010210102
|Variable Name |Location
1010310103
|imm |$encoding[31:20]
10104-
|rs1 |$encoding[19:15]
10104+
|xs1 |$encoding[19:15]
1010510105
|fd |$encoding[11:7]
1010610106
|===
1010710107

@@ -12096,7 +12096,7 @@ No synopsis available
1209612096
Encoding::
1209712097
[wavedrom, ,svg,subs='attributes',width="100%"]
1209812098
....
12099-
{"reg":[{"bits":7,"name": 0x27,"type":2},{"bits":5,"name": "imm[4:0]","type":4},{"bits":3,"name": 0x3,"type":2},{"bits":5,"name": "rs1","type":4},{"bits":5,"name": "rs2","type":4},{"bits":7,"name": "imm[11:5]","type":4}]}
12099+
{"reg":[{"bits":7,"name": 0x27,"type":2},{"bits":5,"name": "imm[4:0]","type":4},{"bits":3,"name": 0x3,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":5,"name": "fs2","type":4},{"bits":7,"name": "imm[11:5]","type":4}]}
1210012100
....
1210112101

1210212102
Description::
@@ -12108,8 +12108,8 @@ Decode Variables::
1210812108
|===
1210912109
|Variable Name |Location
1211012110
|imm |{$encoding[31:25], $encoding[11:7]}
12111-
|rs2 |$encoding[24:20]
12112-
|rs1 |$encoding[19:15]
12111+
|fs2 |$encoding[24:20]
12112+
|xs1 |$encoding[19:15]
1211312113
|===
1211412114

1211512115
Included in::
@@ -12603,7 +12603,7 @@ No synopsis available
1260312603
Encoding::
1260412604
[wavedrom, ,svg,subs='attributes',width="100%"]
1260512605
....
12606-
{"reg":[{"bits":7,"name": 0x27,"type":2},{"bits":5,"name": "imm[4:0]","type":4},{"bits":3,"name": 0x4,"type":2},{"bits":5,"name": "rs1","type":4},{"bits":5,"name": "qs2","type":4},{"bits":7,"name": "imm[11:5]","type":4}]}
12606+
{"reg":[{"bits":7,"name": 0x27,"type":2},{"bits":5,"name": "imm[4:0]","type":4},{"bits":3,"name": 0x4,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":5,"name": "qs2","type":4},{"bits":7,"name": "imm[11:5]","type":4}]}
1260712607
....
1260812608

1260912609
Description::
@@ -12616,7 +12616,7 @@ Decode Variables::
1261612616
|Variable Name |Location
1261712617
|imm |{$encoding[31:25], $encoding[11:7]}
1261812618
|qs2 |$encoding[24:20]
12619-
|rs1 |$encoding[19:15]
12619+
|xs1 |$encoding[19:15]
1262012620
|===
1262112621

1262212622
Included in::
@@ -12923,11 +12923,11 @@ Single-precision floating-point store
1292312923
Encoding::
1292412924
[wavedrom, ,svg,subs='attributes',width="100%"]
1292512925
....
12926-
{"reg":[{"bits":7,"name": 0x27,"type":2},{"bits":5,"name": "imm[4:0]","type":4},{"bits":3,"name": 0x2,"type":2},{"bits":5,"name": "rs1","type":4},{"bits":5,"name": "fs2","type":4},{"bits":7,"name": "imm[11:5]","type":4}]}
12926+
{"reg":[{"bits":7,"name": 0x27,"type":2},{"bits":5,"name": "imm[4:0]","type":4},{"bits":3,"name": 0x2,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":5,"name": "fs2","type":4},{"bits":7,"name": "imm[11:5]","type":4}]}
1292712927
....
1292812928

1292912929
Description::
12930-
The xref:insts:fsw.adoc#udb:doc:inst:fsw[fsw] instruction stores a single-precision floating-point value in _fs2_ to memory at address _rs1_ + _imm_.
12930+
The xref:insts:fsw.adoc#udb:doc:inst:fsw[fsw] instruction stores a single-precision floating-point value in _fs2_ to memory at address _xs1_ + _imm_.
1293112931

1293212932
xref:insts:fsw.adoc#udb:doc:inst:fsw[fsw] does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.
1293312933

@@ -12938,7 +12938,7 @@ Decode Variables::
1293812938
|Variable Name |Location
1293912939
|imm |{$encoding[31:25], $encoding[11:7]}
1294012940
|fs2 |$encoding[24:20]
12941-
|rs1 |$encoding[19:15]
12941+
|xs1 |$encoding[19:15]
1294212942
|===
1294312943

1294412944
Included in::

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