do chore:update_golden_appendix

Author: sudo-apt-abdullah

backends/instructions_appendix/all_instructions.golden.adoc

@@ -569,8 +569,6 @@ Encoding::
 Description::
 This instruction implements the rotation, SubBytes and Round Constant addition steps of the AES
 block cipher Key Schedule.
-
-
 `rnum` must be in the range `0x0..0xA`. The values `0xB..0xF` are reserved.
 
 
@@ -7268,7 +7266,7 @@ Encoding::
 ....
 
 Description::
-The xref:insts:fadd_d.adoc#udb:doc:inst:fadd_d[fadd.d] instruction is analogous to xref:insts:fadd_s.adoc#udb:doc:inst:fadd_s[fadd.s] and performs double-precision floating-point addition between
+The xref:insts:fadd_d.adoc#udb:doc:inst:fadd_d[fadd.d] instruction is analogous to xref:insts:fadd_s.adoc#udb:doc:inst:fadd_s[fadd.s] and performs double-precision floating-point addition of
 `fs1` and `fs2` and writes the final result to `fd`.
 
 
@@ -7387,7 +7385,7 @@ Encoding::
 ....
 
 Description::
-The xref:insts:fadd_s.adoc#udb:doc:inst:fadd_s[fadd.s] instruction performs single-precision floating-point addition of `xs1` and `xs2`
+The xref:insts:fadd_s.adoc#udb:doc:inst:fadd_s[fadd.s] instruction performs single-precision floating-point addition of `fs1` and `fs2`
 and writes the final result to `fd`.
 
 
@@ -10622,8 +10620,7 @@ Encoding::
 ....
 
 Description::
-The
-The xref:insts:fli_q.adoc#udb:doc:inst:fli_q[fli.q] instruction loads one of 32 quad-precision floating-point constants, encoded in the `rs1`
+The xref:insts:fli_q.adoc#udb:doc:inst:fli_q[fli.q] instruction loads one of 32 quad-precision floating-point constants, encoded in the `xs1`
 field, into floating-point register `rd`.
 xref:insts:fli_q.adoc#udb:doc:inst:fli_q[fli.q] is encoded like xref:insts:fmv_w_x.adoc#udb:doc:inst:fmv_w_x[fmv.w.x], but with _fmt_ = Q.
 
@@ -12246,7 +12243,7 @@ Included in::
 == fmv.d.x
 
 Synopsis::
-Floating-Point Move from Integer Register to Double-Precision Register
+Floating-Point Move Double-Precision from Integer Register
 
 Assembly::
 fmv.d.x fd, xs1
@@ -12365,7 +12362,7 @@ Included in::
 == fmv.x.d
 
 Synopsis::
-Floating-Point Move from Double-Precision Register to Integer Register
+Floating-Point Move Double-Precision to Integer Register
 
 Assembly::
 fmv.x.d xd, fs1
@@ -12631,7 +12628,7 @@ Encoding::
 Description::
 The xref:insts:fmvp_q_x.adoc#udb:doc:inst:fmvp_q_x[fmvp.q.x] instruction moves a double-precision number from a pair of integer registers into
 a floating-point register.
-Integer registers xs1 and xs2 supply bits 63:0 and 127:64, respectively; the result is written to
+Integer registers `xs1` and `xs2` supply bits 63:0 and 127:64, respectively; the result is written to
 floating-point register `fd`.
 xref:insts:fmvp_q_x.adoc#udb:doc:inst:fmvp_q_x[fmvp.q.x] is encoded in the OP-FP major opcode with _funct3_=0 and _funct7_=1011011.
 

spec/schemas/schema_defs.json

@@ -102,26 +102,19 @@
         {
           "type": "array",
           "items": {
-            "$ref": "#/$defs/tagged_text"
+            "$ref": "#/$defs/conditional_text"
           }
         }
       ]
     },
-    "tagged_text": {
+    "conditional_text": {
       "type": "object",
-      "required": ["id", "text", "normative"],
+      "required": ["text"],
       "properties": {
-        "id": {
-          "type": "string",
-          "description": "Unique identifier for the statement"
-        },
         "text": {
           "type": "string",
           "description": "Asciidoctor source"
         },
-        "normative": {
-          "type": "boolean"
-        },
         "when()": {
           "type": "string",
           "description": "IDL boolean expression. When true, the text applies"

spec/std/isa/csr/hstatus.yaml

@@ -23,9 +23,7 @@ fields:
     location: 33-32
     base: 64
     description:
-      - id: csr-hstatus-vsxl-values
-        normative: false
-        text: |
+      - text: |
           Determines the effective XLEN in VS-mode. Valid values are:
 
           [separator="!"]
@@ -36,14 +34,12 @@ fields:
           ! 1     ! 64
           !===
         when(): return VSXLEN == 3264;
-      - id: csr-hstatus-vsxl-rv32
-        normative: false
-        text: |
+
+      - text: |
           Because the implementation only supports a single VSXLEN == 32, this field is read-only-0.
         when(): return VSXLEN == 32;
-      - id: csr-hstatus-vsxl-rv64
-        normative: false
-        text: |
+
+      - text: |
           Because the implementation only supports a single VSXLEN == 64, this field is read-only-1.
         when(): return VSXLEN == 64;
 
@@ -77,76 +73,64 @@ fields:
   VTSR:
     location: 22
     long_name: Virtual Trap SRET
-    description:
-      - id: csr-hstatus-vtsr-behavior
-        normative: false
-        text: |
-          When `hstatus.VTSR` is set, executing the `sret` instruction in VS-mode
-          raises a `Virtual Instruction` exception.
-
-          When `hstatus.VTSR` is clear, an `sret` instruction in VS-mode returns control
-          to the mode stored in `vsstatus.SPP`.
+    description: |
+      When `hstatus.VTSR` is set, executing the `sret` instruction in VS-mode
+      raises a `Virtual Instruction` exception.
+
+      When `hstatus.VTSR` is clear, an `sret` instruction in VS-mode returns control
+      to the mode stored in `vsstatus.SPP`.
     type: RW
     reset_value: UNDEFINED_LEGAL
   VTW:
     location: 21
     long_name: Virtual Trap WFI
-    description:
-      - id: csr-hstatus-vtw-behavior
-        normative: false
-        text: |
-          When `hstatus.VTW` is set, a `wfi` instruction executed in VS-mode raises
-          a `Virtual Instruction` exception after waiting an implementation-defined
-          amount of time (which can be 0).
+    description: |
+      When `hstatus.VTW` is set, a `wfi` instruction executed in VS-mode raises
+      a `Virtual Instruction` exception after waiting an implementation-defined
+      amount of time (which can be 0).
 
-          When both `hstatus.VTW` and `mstatus.TW` are clear, a `wfi` instruction
-          executes in VS-mode without a timeout period.
+      When both `hstatus.VTW` and `mstatus.TW` are clear, a `wfi` instruction
+      executes in VS-mode without a timeout period.
 
-          The `wfi` instruction is also affected by `mstatus.TW`, as shown below:
+      The `wfi` instruction is also affected by `mstatus.TW`, as shown below:
 
-          [separator="!",%autowidth,%footer]
-          !===
-          .2+! [.rotate]#`mstatus.TW`# .2+! [.rotate]#`hstatus.VTW`# 4+^.>! `wfi` behavior
-          h! HS-mode h! U-mode h! VS-mode h! VU-mode
+      [separator="!",%autowidth,%footer]
+      !===
+      .2+! [.rotate]#`mstatus.TW`# .2+! [.rotate]#`hstatus.VTW`# 4+^.>! `wfi` behavior
+      h! HS-mode h! U-mode h! VS-mode h! VU-mode
 
-          ! 0 ! 0 ! Wait ! Trap (I) ! Wait ! Trap (V)
-          ! 0 ! 1 ! Wait ! Trap (I) ! Trap (V) ! Trap (V)
-          ! 1 ! - ! Trap (I) ! Trap (I) ! Trap (I) ! Trap (I)
+      ! 0 ! 0 ! Wait ! Trap (I) ! Wait ! Trap (V)
+      ! 0 ! 1 ! Wait ! Trap (I) ! Trap (V) ! Trap (V)
+      ! 1 ! - ! Trap (I) ! Trap (I) ! Trap (I) ! Trap (I)
 
-          6+! Trap (I) - Trap with `Illegal Instruction` code +
-          Trap (V) - Trap with `Virtual Instruction` code
-          !===
+      6+! Trap (I) - Trap with `Illegal Instruction` code +
+      Trap (V) - Trap with `Virtual Instruction` code
+      !===
     type: RW
     reset_value: UNDEFINED_LEGAL
   VTVM:
     location: 20
     long_name: Virtual Trap Virtual Memory
-    description:
-      - id: csr-hstatus-vtvm-behavior
-        normative: false
-        text: |
-          When set, a 'Virtual Instruction` trap occurs when executing an `sfence.vma`, `sinval.vma`,
-          or an explicit CSR access of the `satp` (really `vsatp`) register when in VS-mode.
+    description: |
+      When set, a 'Virtual Instruction` trap occurs when executing an `sfence.vma`, `sinval.vma`,
+      or an explicit CSR access of the `satp` (really `vsatp`) register when in VS-mode.
 
-          When clear, the instructions execute as normal in VS-mode.
+      When clear, the instructions execute as normal in VS-mode.
 
-          Notably, `hstatus.VTVM` does *not* cause `hfence.vvma`, `sfence.w.inval`, or `sfence.inval.ir` to trap.
+      Notably, `hstatus.VTVM` does *not* cause `hfence.vvma`, `sfence.w.inval`, or `sfence.inval.ir` to trap.
 
-          `mstatus.TVM` does not affect the VS-mode instructions controlled by `hstatus.TVTM`.
+      `mstatus.TVM` does not affect the VS-mode instructions controlled by `hstatus.TVTM`.
     type: RW
     reset_value: UNDEFINED_LEGAL
   VGEIN:
     location: 17-12
     long_name: Virtual Guest External Interrupt Number
-    description:
-      - id: csr-hstatus-vgein-behavior
-        normative: false
-        text: |
-          Selects the guest external interrupt source for VS-level external interrupts.
+    description: |
+      Selects the guest external interrupt source for VS-level external interrupts.
 
-          When `hstatus.VGEIN` == 0, no external interrupt source is selected.
+      When `hstatus.VGEIN` == 0, no external interrupt source is selected.
 
-          When `hstatus.VGEIN` != 0, it selects which bit of `hgeip` is currently active in VS-mode.
+      When `hstatus.VGEIN` != 0, it selects which bit of `hgeip` is currently active in VS-mode.
 
     type(): |
       # if NUM_EXTERNAL_GUEST_INTERRUPTS+1 is 63 (because indexing in `hgeip` starts at 1),
@@ -169,92 +153,75 @@ fields:
   HU:
     location: 9
     long_name: Hypervisor in U-mode
-    description:
-      - id: csr-hstatus-hu-behavior
-        normative: false
-        text: |
-          When set, the hypervisor load/store instructions (`hlv`, `hlvx`, and `hsv`) can be
-          executed in U-mode.
+    description: |
+      When set, the hypervisor load/store instructions (`hlv`, `hlvx`, and `hsv`) can be
+      executed in U-mode.
 
-          When clear, the hypervisor load/store instructions cause an `Illegal Instruction` trap.
+      When clear, the hypervisor load/store instructions cause an `Illegal Instruction` trap.
     type: RW
     reset_value: UNDEFINED_LEGAL
   SPVP:
     location: 8
     long_name: Supervisor Previous Virtual Privilege
-    description:
-      - id: csr-hstatus-spvp-behavior
-        normative: false
-        text: |
-          Written by hardware:
+    description: |
+      Written by hardware:
 
-          * When taking a trap into HS-mode from VS-mode or VU-mode, `hstatus.SPVP` is written with the nominal privilege mode
+      * When taking a trap into HS-mode from VS-mode or VU-mode, `hstatus.SPVP` is written with the nominal privilege mode
 
-          Notably, unlike its analog `mstatus.SPP`, `hstatus.SPVP` is *not* cleared when returning from a trap.
+      Notably, unlike its analog `mstatus.SPP`, `hstatus.SPVP` is *not* cleared when returning from a trap.
 
-          Can also be written by software without immediate side-effect.
+      Can also be written by software without immediate side-effect.
 
-          Affects execution by:
+      Affects execution by:
 
-          * Controls the effective privilege level applied to the hypervisor load/store instructions, `hlv`, `hlvx`, and `hsv`.
+      * Controls the effective privilege level applied to the hypervisor load/store instructions, `hlv`, `hlvx`, and `hsv`.
     type: RW
     reset_value: UNDEFINED_LEGAL
   SPV:
     location: 7
     long_name: Supervisor Previous Virtualization Mode
-    description:
-      - id: csr-hstatus-spv-behavior
-        normative: false
-        text: |
-          Written by hardware:
+    description: |
+      Written by hardware:
 
-          * On a trap into HS-mode, hardware writes 1 when the prior mode was VS-mode or VU-mode, and 0 otherwise.
+      * On a trap into HS-mode, hardware writes 1 when the prior mode was VS-mode or VU-mode, and 0 otherwise.
 
-          Can also be written by software without immediate side-effect.
+      Can also be written by software without immediate side-effect.
 
-          Affects execution by:
+      Affects execution by:
 
-          * When an `sret` instruction in executed in HS-mode or M-mode,
-            control returns to VS-mode or VU-mode (as selected by `mstatus.SPP`) when
-            `hstatus.SPV` is 1 and to HS-mode or U-mode otherwise.
+      * When an `sret` instruction in executed in HS-mode or M-mode,
+        control returns to VS-mode or VU-mode (as selected by `mstatus.SPP`) when
+        `hstatus.SPV` is 1 and to HS-mode or U-mode otherwise.
     type: RW
     reset_value: UNDEFINED_LEGAL
   GVA:
     location: 6
     long_name: Guest Virtual Address
-    description:
-      - id: csr-hstatus-gva-behavior
-        normative: false
-        text: |
-          Written by hardware whenever a trap is taken into HS-mode:
+    description: |
+      Written by hardware whenever a trap is taken into HS-mode:
 
-          * Writes 1 when a trap causes a guest virtual address to be written into `stval` (`Breakpoint`, `* Address Misaligned`, `* Access Fault`, `* Page Fault`, or `* Guest-Page Fault`).
-          * Writes 0 otherwise
+      * Writes 1 when a trap causes a guest virtual address to be written into `stval` (`Breakpoint`, `* Address Misaligned`, `* Access Fault`, `* Page Fault`, or `* Guest-Page Fault`).
+      * Writes 0 otherwise
 
-          Does not affect execution.
+      Does not affect execution.
     type: RW
     reset_value: UNDEFINED_LEGAL
   VSBE:
     location: 5
     long_name: VS-mode Big Endian
     description:
-      - id: csr-hstatus-vgein-behavior
-        normative: false
-        text: |
+      - text: |
           Controls the endianness of data VS-mode (0 = little, 1 = big).
           Instructions are always little endian, regardless of the data setting.
 
-      - id: csr-hstatus-vgein-little-endian
-        normative: false
-        text: |
+      - text: |
           Since the CPU does not support big endian in VS-mode, this is hardwired to 0.
         when(): return VS_MODE_ENDIANNESS == "little";
 
-      - id: csr-hstatus-vgein-big-endian
-        normative: false
-        text: |
+      - text: |
           Since the CPU does not support little endian in VS-mode, this is hardwired to 1.
         when(): return VS_MODE_ENDIANNESS == "big";
+
     type(): |
       if (VS_MODE_ENDIANNESS == "dynamic") {
         # mode is mutable