Merge branch 'main' into H_CSRs

Author: Shehrozkashif

Rakefile

@@ -272,7 +272,7 @@ namespace :test do
 
   task schema: "#{$root}/.stamps/resolve-_.stamp" do
     puts "Checking arch files against schema.."
-    Architecture.new("#{$root}/gen/resolved_arch/_").validate(show_progress: true)
+    cfg_arch_for("_").validate(show_progress: true)
     puts "All files validate against their schema"
   end
 

arch/csr/H/hgeie.yaml

@@ -63,6 +63,6 @@ fields:
       return NUM_EXTERNAL_GUEST_INTERRUPTS > 0 ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: UNDEFINED_LEGAL
     sw_write(csr_value): |
-      return ((1 << NUM_EXTERNAL_GUEST_INTERRUPTS) - 1) & csr_value.GEI_ENABLE;
+      return ((MXLEN'1 << NUM_EXTERNAL_GUEST_INTERRUPTS) - 1) & csr_value.GEI_ENABLE;
     description: |
       Enable bits; see description of hgeie

arch/csr/H/hgeip.yaml

@@ -56,4 +56,4 @@ fields:
     type: RO
     reset_value: UNDEFINED_LEGAL
     description: |
-      Enable bits; see description of hgeip
+      Pending bits; see description of hgeip

arch/csr/H/vsie.yaml

@@ -45,7 +45,16 @@ fields:
     alias: hie.VSSIE[0]
     description: |
       SSIE. Read-only zero when hideleg[2] is 0. Else, alias of hie.VSSIE.
-
+      sw_read(): |
+          if (CSR[hideleg].S == 1) {
+            return CSR[hie].VSSIE[0];
+          } else {
+            return 0;
+          }
+      sw_write(csr_value): |
+      if (CSR[hideleg].S == 1) {
+        CSR[hie].VSSIE[0] = csr_value.VSSIE & ((1 << NUM_VSSI) - 1);
+      }
   STIE:
     location: 5
     type: RW-H

arch/csr/H/vsip.yaml

@@ -38,7 +38,16 @@ fields:
 
       Indicates a pending software interrupt at the supervisor level.
       Read-only zero when `hideleg[2] == 0`, else aliased to `hip.VSSIP[0]`.
-
+      sw_read(): |
+        if (CSR[hideleg].S == 1) {
+          return CSR[hip].VSSIP[0];
+        } else {
+          return 0;
+        }
+       sw_write(csr_value): |
+          if (CSR[hideleg].S == 1) {
+            CSR[hip].VSSIP[0] = csr_value.VSSIP & ((MXLEN'1 << NUM_VSSI) - 1);
+        }
   STIP:
     location: 5
     type: RW-H

arch/csr/H/vsscratch.yaml

@@ -21,4 +21,10 @@ description:
 priv_mode: VS
 length: VSXLEN
 definedBy: H
-fields: {}
+fields:
+  SCRATCH:
+    type: RW
+    reset_value: 0
+    location: 0
+    description: |
+      Virtual supervisor scratch register.

arch/ext/Sm.yaml

@@ -404,6 +404,7 @@ params:
       minimum: 0
       maximum: 0xFFFFFFFFFFFFFFFF
     when:
+      name: Sm
       version: ">= 1.12.0"
   PMA_GRANULARITY:
     description: |

arch/inst/C/c.add.yaml

@@ -5,20 +5,20 @@ kind: instruction
 name: c.add
 long_name: Add
 description: |
-  Add the value in rs2 to rd, and store the result in rd.
-  C.ADD expands into `add rd, rd, rs2`.
+  Add the value in xs2 to xd, and store the result in xd.
+  C.ADD expands into `add xd, xd, xs2`.
 definedBy:
   anyOf:
     - C
     - Zca
-assembly: xd, rs2
+assembly: xd, xs2
 encoding:
   match: 1001----------10
   variables:
-    - name: rs2
+    - name: xs2
       location: 6-2
       not: 0
-    - name: rd
+    - name: xd
       location: 11-7
       not: 0
 access:
@@ -27,9 +27,9 @@ access:
   vs: always
   vu: always
 operation(): |
-  XReg t0 = X[rd];
-  XReg t1 = X[rs2];
-  X[rd] = t0 + t1;
+  XReg t0 = X[xd];
+  XReg t1 = X[xs2];
+  X[xd] = t0 + t1;
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

arch/inst/C/c.addw.yaml

@@ -5,31 +5,31 @@ kind: instruction
 name: c.addw
 long_name: Add word
 description: |
-  Add the 32-bit values in rs2 from rd, and store the result in rd.
-  The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15).
-  C.ADDW expands into `addw rd, rd, rs2`.
+  Add the 32-bit values in xs2 from xd, and store the result in xd.
+  The xd and xs2 register indexes should be used as xd+8 and xs2+8 (registers x8-x15).
+  C.ADDW expands into `addw xd, xd, xs2`.
 definedBy:
   anyOf:
     - C
     - Zca
 base: 64
-assembly: xd, rs2
+assembly: xd, xs2
 encoding:
   match: 100111---01---01
   variables:
-    - name: rs2
+    - name: xs2
       location: 4-2
-    - name: rd
+    - name: xd
       location: 9-7
 access:
   s: always
   u: always
   vs: always
   vu: always
 operation(): |
-  Bits<32> t0 = X[creg2reg(rd)][31:0];
-  Bits<32> t1 = X[creg2reg(rs2)][31:0];
-  X[creg2reg(rd)] = $signed(t0 + t1);
+  Bits<32> t0 = X[creg2reg(xd)][31:0];
+  Bits<32> t1 = X[creg2reg(xs2)][31:0];
+  X[creg2reg(xd)] = $signed(t0 + t1);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

arch/inst/C/c.and.yaml

@@ -5,30 +5,30 @@ kind: instruction
 name: c.and
 long_name: And
 description: |
-  And rd with rs2, and store the result in rd
-  The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15).
-  C.AND expands into `and rd, rd, rs2`.
+  And xd with xs2, and store the result in xd
+  The xd and xs2 register indexes should be used as xd+8 and xs2+8 (registers x8-x15).
+  C.AND expands into `and xd, xd, xs2`.
 definedBy:
   anyOf:
     - C
     - Zca
-assembly: xd, rs2
+assembly: xd, xs2
 encoding:
   match: 100011---11---01
   variables:
-    - name: rs2
+    - name: xs2
       location: 4-2
-    - name: rd
+    - name: xd
       location: 9-7
 access:
   s: always
   u: always
   vs: always
   vu: always
 operation(): |
-  XReg t0 = X[creg2reg(rd)];
-  XReg t1 = X[creg2reg(rs2)];
-  X[creg2reg(rd)] = t0 & t1;
+  XReg t0 = X[creg2reg(xd)];
+  XReg t1 = X[creg2reg(xs2)];
+  X[creg2reg(xd)] = t0 & t1;
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>