fix(data): update extension descriptions to better match spec

spec/std/isa/ext/B.yaml

@@ -7,7 +7,7 @@ $schema: "ext_schema.json#"
 kind: extension
 name: B
 type: unprivileged
-long_name: Bitmanipulation instructions
+long_name: Bit Manipulation
 company:
   name: RISC-V International
   url: https://riscv.org

spec/std/isa/ext/M.yaml

@@ -7,7 +7,7 @@ $schema: "ext_schema.json#"
 kind: extension
 name: M
 type: unprivileged
-long_name: Integer multiply and divide instructions
+long_name: Integer multiply and divide
 versions:
   - version: "2.0.0"
     state: ratified

spec/std/isa/ext/Sha.yaml

@@ -7,7 +7,7 @@ $schema: "ext_schema.json#"
 kind: extension
 name: Sha
 type: privileged
-long_name: The augmented hypervisor extension
+long_name: Augmented hypervisor
 description: |
   *Sha* comprises the following extensions:
 

spec/std/isa/ext/Shgatpa.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Shgatpa
-long_name: hgtap profile requirements
+long_name: SvNNx4 mode supported for all modes supported by Supervisor Address Translation and Protection, as well as Bare
 description: |
   For each supported virtual memory scheme SvNN supported in
   `satp`, the corresponding hgatp SvNNx4 mode must be supported.  The

spec/std/isa/ext/Shtvala.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Shtvala
-long_name: htval profile requirements
+long_name: Hypervisor Trap Value provides all needed values
 description: |
   htval must be written with the faulting virtual address
   for load, store, and instruction page-fault, access-fault, and

spec/std/isa/ext/Shvsatpa.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Shvsatpa
-long_name: vstap translation mode requirements
+long_name: Virtual Supervisor Address Translation and Protection supports all modes supported by Supervisor Address Translation and Protection
 description: |
   All translation modes supported in the `satp` CSR must be supported in the `vsatp` CSR.
 

spec/std/isa/ext/Shvstvala.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Shvstvala
-long_name: vstval profile requirements
+long_name: Virtual Supervisor Trap Value provides all needed values
 description: |
   vstval must be written with the faulting virtual address
   for load, store, and instruction page-fault, access-fault, and

spec/std/isa/ext/Shvstvecd.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Shvstvecd
-long_name: vstvec profile requirements
+long_name: Virtual Supervisor Trap Vector Base Address supports Direct mode
 description: |
   `vstvec.MODE` must be capable of holding the value 0 (Direct).
   When `vstvec.MODE`=Direct, `vstvec.BASE` must be capable of holding

spec/std/isa/ext/Smcsrind.yaml

@@ -7,7 +7,7 @@ $schema: "ext_schema.json#"
 kind: extension
 name: Smcsrind
 type: privileged
-long_name: Machine Indirect CSR Access (Smcsrind)
+long_name: Machine-mode Indirect CSR Access
 description: |
   Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as
   part of the Smaia/Ssaia extensions, in order to make it available for use by other extensions without creating

spec/std/isa/ext/Smdbltrp.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Smdbltrp
-long_name: Double trap
+long_name: Double trap in M-mode
 description: |
   The `Smdbltrp` extension addresses a double trap in M-mode.
   When the `Smrnmi` extension is implemented, it enables invocation of the RNMI handler on a

spec/std/isa/ext/Sscounterenw.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Sscounterenw
-long_name: Supervisor counter enable
+long_name: Support writeable enables for any supported counter
 description: |
   For any hpmcounter that is not read-only zero, the corresponding bit in `scounteren` must be writable.
 

spec/std/isa/ext/Sscsrind.yaml

@@ -7,7 +7,7 @@ $schema: "ext_schema.json#"
 kind: extension
 name: Sscsrind
 type: privileged
-long_name: Supervisor Indirect CSR Access (Sscsrind)
+long_name: Supervisor-mode Indirect CSR Access
 description: |
   Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as
   part of the Smaia/Ssaia extensions, in order to make it available for use by other extensions without creating

spec/std/isa/ext/Ssstrict.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Ssstrict
-long_name: Unimplemented reserved encodings trap and no no-conforming extensions
+long_name: Unimplemented reserved encodings trap and no non-conforming extensions
 type: privileged
 description: |
   No non-conforming extensions are present.  Attempts to

spec/std/isa/ext/Sstvala.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Sstvala
-long_name: "`stval` requirements for RVA profiles"
+long_name: "Supervisor Trap Value provides all needed values"
 description: |
   `stval` must be written with the faulting virtual address for load, store,
   and instruction page-fault, access-fault, and misaligned exceptions,

spec/std/isa/ext/Svnapot.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Svnapot
-long_name: Naturally-aligned Power of Two Translation Contiguity
+long_name: Naturally Aligned Power-of-Two Translation Contiguity
 type: privileged
 description: |
   In Sv39, Sv48, and Sv57, when a PTE has N=1, the PTE represents a

spec/std/isa/ext/Svvptc.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Svvptc
-long_name: Guarantees visibility of PTE transitions from invalid to valid
+long_name: Guarantee visibility of PTE transitions from invalid to valid
 description: |
   When the Svvptc extension is implemented, explicit stores by a hart that update
   the Valid bit of leaf and/or non-leaf PTEs from 0 to 1 and are visible to a hart

spec/std/isa/ext/V.yaml

@@ -7,13 +7,13 @@ $schema: "ext_schema.json#"
 kind: extension
 name: V
 type: unprivileged
-long_name: Variable-length vector
+long_name: Vector Operations
 versions:
   - version: "1.0.0"
     state: ratified
     ratification_date: null
 description: |
-  TODO
+  General support for data-parallel execution.
 params:
   MUTABLE_MISA_V:
     description: |

spec/std/isa/ext/Za128rs.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Za128rs
-long_name: Reservation set requirement for RVA profiles
+long_name: Reservation set size of at most 128 bytes
 type: unprivileged
 description: |
   Reservation sets must be contiguous, naturally aligned, and at most 128 bytes in size.

spec/std/isa/ext/Za64rs.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Za64rs
-long_name: Reservation set requirement for RVA profiles
+long_name: Reservation set size of at most 64 bytes
 type: unprivileged
 description: |
   Reservation sets must be contiguous, naturally aligned, and at most 64 bytes in size.

spec/std/isa/ext/Zalasr.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Zalasr
-long_name: Atomic, Load-Acquire Store-Release
+long_name: Atomic Load-Acquire and Store-Release
 description: |
   load-acquire and store-release instructions.
 type: unprivileged

spec/std/isa/ext/Zalrsc.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Zalrsc
-long_name: Atomic read-modify-write instructions
+long_name: Load-Reserved/Store-Conditional Instructions
 type: unprivileged
 versions:
   - version: "1.0.0"

spec/std/isa/ext/Zama16b.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Zama16b
-long_name: Misaligned load/store/AMO within aligned 16-byte address are atomic
+long_name: Misaligned load/store/AMO within aligned 16-byte boundaries are atomic
 type: unprivileged
 description: |
   Misaligned loads, stores, and AMOs to main memory regions that do not cross a

spec/std/isa/ext/Zba.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Zba
-long_name: Address generation instructions
+long_name: Address generation
 description: |
   The Zba instructions can be used to accelerate the generation of addresses that index into
   arrays of basic types (halfword, word, doubleword) using both unsigned word-sized and

spec/std/isa/ext/Zbb.yaml

@@ -6,9 +6,9 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Zbb
-long_name: Basic bit manipulation
+long_name: Basic bit-manipulation
 description: |
-  Basic bit manipulation
+  Basic bit-manipulation
 type: unprivileged
 company:
   name: RISC-V International

spec/std/isa/ext/Zbc.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Zbc
-long_name: Carry-less multiplication scalar instructions
+long_name: Carry-less multiplication
 description: |
   Carry-less multiplication is the multiplication in the polynomial ring over GF(2).
 type: unprivileged

spec/std/isa/ext/Zca.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Zca
-long_name: C instructions excluding floating-point
+long_name: C instructions excluding floating-point loads/stores
 description: |
   The Zca extension is added as way to refer to instructions in the `C` extension that do not
   include the floating-point loads and stores.

spec/std/isa/ext/Zcd.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Zcd
-long_name: Compressed instructions for double precision floating point
+long_name: Compressed double-precision floating-point loads/stores
 description: |
   Zcd is the existing set of compressed double precision floating point loads and stores:
   `c.fld`, `c.fldsp`, `c.fsd`, `c.fsdsp`.

spec/std/isa/ext/Zcf.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Zcf
-long_name: Compressed instructions for single precision floating point
+long_name: Compressed single-precision floating-point loads/stores
 description: |
   Zcf is the existing set of compressed single precision floating point loads and stores (RV32 only):
   `c.flw`, `c.flwsp`, `c.fsw`, `c.fswsp`.

spec/std/isa/ext/Zcmop.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Zcmop
-long_name: 16-bit May-be Operations
+long_name: Compressed May-Be-Operations
 description: |
   The "Zcmop" extension, which defines eight 16-bit MOP
   instructions named C.MOP.__n__, where __n__ is an odd integer between 1 and

spec/std/isa/ext/Zcmp.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Zcmp
-long_name: 16-bit Push/Pop instructions
+long_name: Complex PUSH/POP and Double Move
 description: |
   The Zcmp extension is a set of instructions which may be executed as a series of existing 32-bit RISC-V instructions.
 

spec/std/isa/ext/Zcmt.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Zcmt
-long_name: 16-bit Table Jump
+long_name: Table Jump
 description: |
   Zcmt adds the table jump instructions and also adds the jvt CSR. The jvt CSR requires a
   state enable if Smstateen is implemented. See <<csrs-jvt>> for details.

spec/std/isa/ext/Zfa.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Zfa
-long_name: Extension for Additional Floating-Point Instructions
+long_name: Additional Floating-Point Instructions
 description: |
   `Zfa` adds instructions for immediate loads, IEEE 754-2019 minimum and maximum operations,
   round-to-integer operations, and quiet floating-point comparisons.

spec/std/isa/ext/Zfhmin.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Zfhmin
-long_name: Minimal half-precision Floating-point
+long_name: Minimal half-precision floating-point
 description: |
   `Zfhmin` provides
   minimal support for 16-bit half-precision binary floating-point

spec/std/isa/ext/Zicbom.yaml

@@ -6,8 +6,8 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Zicbom
-long_name: Cache block management instructions
-description: Cache block management instructions
+long_name: Cache-block management instructions
+description: Cache-block management instructions
 type: unprivileged
 versions:
   - version: "1.0.0"

spec/std/isa/ext/Zicbop.yaml

@@ -6,8 +6,8 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Zicbop
-long_name: Cache block prefetch
-description: Cache block prefetch instruction
+long_name: Cache-block prefetch
+description: Cache-block prefetch instructions
 type: unprivileged
 versions:
   - version: "1.0.0"

spec/std/isa/ext/Zicboz.yaml

@@ -6,8 +6,8 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Zicboz
-long_name: Cache block zero instruction
-description: Cache block zero instruction
+long_name: Cache-block zero instruction
+description: Cache-block zero instruction
 type: unprivileged
 versions:
   - version: "1.0.0"

spec/std/isa/ext/Ziccamoa.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Ziccamoa
-long_name: Main memory atomicity requirement for RVA profiles
+long_name: Main memory supports all atomics in A extension
 type: unprivileged
 description: |
   Main memory regions with both the cacheability and coherence PMAs must support AMOArithmetic.

spec/std/isa/ext/Ziccif.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Ziccif
-long_name: Main memory fetch requirement for RVA profiles
+long_name: Main memory supports instruction fetch with atomicity requirement
 type: unprivileged
 description: |
   Main memory regions with both the cacheability and coherence PMAs must support instruction

spec/std/isa/ext/Zicclsm.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Zicclsm
-long_name: Main memory misaligned requirement for RVA profiles
+long_name: "Main memory supports misaligned loads/stores"
 type: unprivileged
 description: |
   Misaligned loads and stores to main memory regions with both the cacheability and coherence

spec/std/isa/ext/Ziccrse.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Ziccrse
-long_name: Main memory reservability requirement for RVA profiles
+long_name: Main memory supports forward progress on LR/SC sequences
 type: unprivileged
 description: |
   Main memory regions with both the cacheability and coherence PMAs must support RsrvEventual.

spec/std/isa/ext/Zicfilp.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Zicfilp
-long_name: Landing Pads
+long_name: Landing Pad
 description: |
   TODO
 type: unprivileged

spec/std/isa/ext/Zicntr.yaml

@@ -6,8 +6,10 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Zicntr
-long_name: Architectural performance counters
-description: Architectural performance counters
+long_name: Base Counters and Timers
+description: |
+  The CYCLE, TIME, and INSTRET counters, which have dedicated functions
+  (cycle count, real-time clock, and instructions retired, respectively).
 type: unprivileged
 versions:
   - version: "2.0.0"