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4 changes: 2 additions & 2 deletions arch/csr/menvcfg.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -247,8 +247,8 @@ menvcfg:
type: RW-R
sw_write(csr_value): |
if ((csr_value.CBIE == 0) ||
(ALLOW_CBO_INVAL_UPGRADE_TO_FLUSH && (csr_value.CBIE == 1)) ||
(csr_value.CBIE == 3)) {
(csr_value.CBIE == 1) ||
((!FORCE_UPGRADE_CBO_INVAL_TO_FLUSH) && (csr_value.CBIE == 3))) {
return csr_value.CBIE;
} else {
return CSR[menvcfg].CBIE;
Expand Down
10 changes: 5 additions & 5 deletions arch/ext/Zicbom.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -15,12 +15,12 @@ Zicbom:
also_defined_in: [Zicboz, Zicbop]
schema:
type: integer
ALLOW_CBO_INVAL_UPGRADE_TO_FLUSH:
FORCE_UPGRADE_CBO_INVAL_TO_FLUSH:
description: |
When true, an implementation can (when `menvcfg.CBIE` == `01`) upgrade a `cbo.inval`
instruction to a `cbo.flush`.
When true, an implementation prohibits setting `menvcfg.CBIE` == `11` such that all `cbo.inval`
instructions either trap (when `menvcfg.CBIE` == '00') or flush (when `menvcfg.CBIE` == '01').

When false, an implementation does not support the upgrade, and the value '01' cannot be
written to `menvcfg.CBIE`.
When false, an implementation allows a true INVAL operation for `cbo.inval`, and thus supports
the setting `menvcfg.CBIE` == `11`.
schema:
type: boolean
2 changes: 1 addition & 1 deletion cfgs/generic_rv64/params.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -514,4 +514,4 @@ params:
MSTATUS_FS_WRITEABLE: true
MSTATUS_TVM_IMPLEMENTED: true
HW_MSTATUS_FS_DIRTY_UPDATE: precise
ALLOW_CBO_INVAL_UPGRADE_TO_FLUSH: true
FORCE_UPGRADE_CBO_INVAL_TO_FLUSH: true
2 changes: 1 addition & 1 deletion ext/riscv-isa-manual
Submodule riscv-isa-manual updated 54 files
+4 −4 .github/workflows/merge-and-release.yml
+14 −7 Makefile
+1 −0 marchid.md
+1 −6 src/b-st-ext.adoc
+3 −3 src/c-st-ext.adoc
+1 −1 src/cmo.adoc
+3 −5 src/hypervisor.adoc
+0 −0 src/images/bytefield/counteren.edn
+0 −0 src/images/bytefield/counterinh.edn
+0 −0 src/images/bytefield/cust-sys-instr.edn
+0 −0 src/images/bytefield/hpmevents.edn
+0 −0 src/images/bytefield/marchid.edn
+0 −0 src/images/bytefield/mcausereg.edn
+0 −0 src/images/bytefield/mconfigptrreg.edn
+0 −0 src/images/bytefield/medeleg.edn
+0 −0 src/images/bytefield/mepcreg.edn
+0 −0 src/images/bytefield/mhartid.edn
+0 −0 src/images/bytefield/mideleg.edn
+0 −0 src/images/bytefield/miereg-standard.edn
+0 −0 src/images/bytefield/mimpid.edn
+0 −0 src/images/bytefield/mipreg-standard.edn
+0 −0 src/images/bytefield/mnscratch.edn
+0 −0 src/images/bytefield/mscratch.edn
+0 −0 src/images/bytefield/mseccfg.edn
+0 −0 src/images/bytefield/mtime.edn
+0 −0 src/images/bytefield/mtimecmp.edn
+0 −0 src/images/bytefield/mtvalreg.edn
+0 −0 src/images/bytefield/mtvec.edn
+0 −0 src/images/bytefield/mvendorid.edn
+0 −0 src/images/bytefield/pmp-rv32.edn
+0 −0 src/images/bytefield/pmp-rv64.edn
+0 −0 src/images/bytefield/pmpaddr-rv32.edn
+0 −0 src/images/bytefield/pmpaddr-rv64.edn
+0 −0 src/images/bytefield/pmpcfg.edn
+0 −0 src/images/bytefield/rvc-instr-quad0.edn
+0 −0 src/images/bytefield/rvc-instr-quad1.edn
+0 −0 src/images/bytefield/rvc-instr-quad2.edn
+0 −11 src/j-st-ext.adoc
+34 −40 src/machine.adoc
+2 −2 src/mm-eplan.adoc
+61 −47 src/naming.adoc
+4 −2 src/priv-cfi.adoc
+7 −7 src/priv-csrs.adoc
+11 −11 src/priv-preface.adoc
+17 −0 src/resources/riscv-spec.bib
+6 −5 src/riscv-privileged.adoc
+0 −1 src/riscv-unprivileged.adoc
+2 −2 src/rnmi.adoc
+3 −2 src/scalar-crypto.adoc
+1 −1 src/smcntrpmf.adoc
+5 −3 src/sscofpmf.adoc
+12 −11 src/supervisor.adoc
+11 −11 src/unpriv-cfi.adoc
+297 −0 src/zpm.adoc
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