Fix CSRRS

arch/inst/A/sc.d.yaml

@@ -100,6 +100,7 @@ description: |
   with both bits clear, but may result in lower performance.
 definedBy:
   anyOf: [A, Zalrsc]
+base: 64
 assembly: xd, xs2, xs1
 encoding:
   match: 00011------------011-----0101111

arch/inst/C/c.ld.yaml

@@ -13,6 +13,7 @@ definedBy:
   anyOf:
     - C
     - Zca
+base: 64
 assembly: xd, imm(xs1)
 encoding:
   match: 011-----------00

arch/inst/C/c.sd.yaml

@@ -13,6 +13,7 @@ definedBy:
   anyOf:
     - C
     - Zca
+base: 64
 assembly: xs2, imm(xs1)
 encoding:
   match: 111-----------00

arch/inst/C/c.slli.yaml

@@ -11,6 +11,7 @@ definedBy:
   anyOf:
     - C
     - Zca
+base: 64
 assembly: xd, shamt
 encoding:
   match: 000-----------10

arch/inst/C/c.srai.yaml

@@ -12,6 +12,7 @@ definedBy:
   anyOf:
     - C
     - Zca
+base: 64
 assembly: xd, shamt
 encoding:
   match: 100-01--------01

arch/inst/C/c.srli.yaml

@@ -12,6 +12,7 @@ definedBy:
   anyOf:
     - C
     - Zca
+base: 64
 assembly: xd, shamt
 encoding:
   match: 100-00--------01

arch/inst/M/divuw.yaml

@@ -11,6 +11,7 @@ description: |
 
   If the value in rs2 is zero, rd is written with all 1s.
 definedBy: M
+base: 64
 assembly: xd, xs1, xs2
 encoding:
   match: 0000001----------101-----0111011

arch/inst/M/divw.yaml

@@ -15,6 +15,7 @@ description: |
   Division resulting in signed overflow (when most negative number is divided by -1)
   will put the most negative number into rd;
 definedBy: M
+base: 64
 assembly: xd, xs1, xs2
 encoding:
   match: 0000001----------100-----0111011

arch/inst/M/mulw.yaml

@@ -17,6 +17,7 @@ description: |
   an alternative is to shift both arguments left by 32 bits, then use MULH[[S]U].
 definedBy:
   anyOf: [M, Zmmul]
+base: 64
 assembly: xd, xs1, xs2
 encoding:
   match: 0000001----------000-----0111011

arch/inst/M/remuw.yaml

@@ -10,6 +10,7 @@ description: |
 
   If the value in rs2 is zero, rd gets the sign-extended value in rs1.
 definedBy: M
+base: 64
 assembly: xd, xs1, xs2
 encoding:
   match: 0000001----------111-----0111011

arch/inst/M/remw.yaml

@@ -12,6 +12,7 @@ description: |
 
   If the result of the division overflows, write zero into rd;
 definedBy: M
+base: 64
 assembly: xd, xs1, xs2
 encoding:
   match: 0000001----------110-----0111011

arch/inst/Zicsr/csrrs.yaml

@@ -16,7 +16,7 @@ description: |
 definedBy: Zicsr
 assembly: xd, xs1, csr
 encoding:
-  match: -----------------010-----0010011
+  match: -----------------010-----1110011
   variables:
     - name: csr
       location: 31-20