Implement vset* and vector CSRs

arch/inst/V/vsetivli.yaml

@@ -3,9 +3,11 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vsetivli
-long_name: No synopsis available.
+long_name: Set vector configuration (immediate immediate).
 description: |
-  No description available.
+  Vset (i,i) allows rapid configuration of the values in vl and vtype CSRs to match application
+  needs. The vsetvl instruction sets the vtype and vl CSRs based on the arguments, and writes
+  the new value of vl into rd.
 definedBy: V
 assembly: xd, imm
 encoding:
@@ -24,7 +26,19 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  XReg state = vector_state();
+  XReg VLMAX = state.log2_multiplier * VLEN * state.sew;
+  # todo: state.lmul_type
 
+  if (xs1 < VLMAX){
+    CSR[vl] = uimm;
+  } else {
+    CSR[vl] = VLMAX;
+  }
+
+  CSR[vtype] = zimm11;
+  X[rd] = CSR[vl];
+  CSR[vstart] = 0;
 sail(): |
   {
     let VLEN_pow      = get_vlen_pow();

arch/inst/V/vsetvl.yaml

@@ -3,9 +3,11 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vsetvl
-long_name: No synopsis available.
+long_name: Set vector configuration (register register).
 description: |
-  No description available.
+  Vset (r,r) allows rapid configuration of the values in vl and vtype CSRs to match application
+  needs. The vsetvl instruction sets the vtype and vl CSRs based on the contents of the argument
+  registers rs1 and rs2, and writes the new value of vl into rd.
 definedBy: V
 assembly: xs2, xs1, xd
 encoding:
@@ -24,3 +26,85 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  XReg state = vector_state();
+  XReg VLMAX = state.log2_multiplier * VLEN * state.sew;
+  # todo: state.lmul_type
+
+  if (xs1 < VLMAX){
+    CSR[vl] = X[rs1];
+  } else {
+    CSR[vl] = VLMAX;
+  }
+
+  CSR[vtype] = X[rs2];
+  X[rd] = CSR[vl];
+  CSR[vstart] = 0;
+sail(): |
+  {
+    let VLEN_pow      = get_vlen_pow();
+    let ELEN_pow      = get_elen_pow();
+    let LMUL_pow_ori  = get_lmul_pow();
+    let SEW_pow_ori   = get_sew_pow();
+    let ratio_pow_ori = SEW_pow_ori - LMUL_pow_ori;
+
+    /* set vtype */
+    match op {
+      VSETVLI => {
+        vtype->bits() = 0b0 @ zeros(sizeof(xlen) - 9) @ ma @ ta @ sew @ lmul
+      },
+      VSETVL  => {
+        let rs2 : regidx = sew[1 .. 0] @ lmul;
+        vtype->bits() = X(rs2)
+      }
+    };
+
+    /* check legal SEW and LMUL and calculate VLMAX */
+    let LMUL_pow_new = get_lmul_pow();
+    let SEW_pow_new  = get_sew_pow();
+    if SEW_pow_new > LMUL_pow_new + ELEN_pow then {
+      /* Note: Implementations can set vill or trap if the vtype setting is not supported.
+       * TODO: configuration support for both solutions
+       */
+      vtype->bits() = 0b1 @ zeros(sizeof(xlen) - 1); /* set vtype.vill */
+      vl = zeros();
+      print_reg("CSR vtype <- " ^ BitStr(vtype.bits()));
+      print_reg("CSR vl <- " ^ BitStr(vl));
+      return RETIRE_SUCCESS
+    };
+    let VLMAX = int_power(2, VLEN_pow + LMUL_pow_new - SEW_pow_new);
+
+    /* set vl according to VLMAX and AVL */
+    if (rs1 != 0b00000) then { /* normal stripmining */
+      let rs1_val = X(rs1);
+      let AVL = unsigned(rs1_val);
+      vl = if AVL <= VLMAX then to_bits(sizeof(xlen), AVL)
+           else if AVL < 2 * VLMAX then to_bits(sizeof(xlen), (AVL + 1) / 2)
+           else to_bits(sizeof(xlen), VLMAX);
+      /* Note: ceil(AVL / 2) <= vl <= VLMAX when VLMAX < AVL < (2 * VLMAX)
+       * TODO: configuration support for either using ceil(AVL / 2) or VLMAX
+       */
+      X(rd) = vl;
+    } else if (rd != 0b00000) then { /* set vl to VLMAX */
+      let AVL = unsigned(ones(sizeof(xlen)));
+      vl = to_bits(sizeof(xlen), VLMAX);
+      X(rd) = vl;
+    } else { /* keep existing vl */
+      let AVL = unsigned(vl);
+      let ratio_pow_new = SEW_pow_new - LMUL_pow_new;
+      if (ratio_pow_new != ratio_pow_ori) then {
+        /* Note: Implementations can set vill or trap if the vtype setting is not supported.
+         * TODO: configuration support for both solutions
+         */
+        vtype->bits() = 0b1 @ zeros(sizeof(xlen) - 1); /* set vtype.vill */
+        vl = zeros();
+      }
+    };
+    print_reg("CSR vtype <- " ^ BitStr(vtype.bits()));
+    print_reg("CSR vl <- " ^ BitStr(vl));
+
+    /* reset vstart to 0 */
+    vstart = zeros();
+    print_reg("CSR vstart <- " ^ BitStr(vstart));
+
+    RETIRE_SUCCESS
+  }

arch/inst/V/vsetvli.yaml

@@ -3,9 +3,11 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vsetvli
-long_name: No synopsis available.
+long_name: Set vector configuration (register immediate).
 description: |
-  No description available.
+  Vset (r,i) allows rapid configuration of the values in vl and vtype CSRs to match application
+  needs. The vsetvl instruction sets the vtype and vl CSRs based on the contents of the argument
+  register rs1 and immediate, and writes the new value of vl into rd.
 definedBy: V
 assembly: xs1, xd, imm
 encoding:
@@ -24,7 +26,19 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  XReg state = vector_state();
+  XReg VLMAX = state.log2_multiplier * VLEN * state.sew;
+  # todo: state.lmul_type
 
+  if (xs1 < VLMAX){
+    CSR[vl] = X[rs1];
+  } else {
+    CSR[vl] = VLMAX;
+  }
+
+  CSR[vtype] = zimm11;
+  X[rd] = CSR[vl];
+  CSR[vstart] = 0;
 sail(): |
   {
     let VLEN_pow      = get_vlen_pow();

arch/isa/vec.idl

@@ -0,0 +1,50 @@
+%version: 1.0
+
+# - test suite?
+# - Vector params (there will be many)
+# - Vector state
+# - Order (might be dictated somewhat by test suite)
+#   - vset*
+#   - integer arith (vadd/vsub/vrsub(.vv,.vx,.vi), compare, min, max)
+#   - integer widening arith ()
+
+# the vector register file
+Bits<VLEN> v[32] = [0, 0, 0, 0, 0, 0, 0, 0,
+                    0, 0, 0, 0, 0, 0, 0, 0,
+                    0, 0, 0, 0, 0, 0, 0, 0,
+                    0, 0, 0, 0, 0, 0, 0, 0];
+
+enum VectorLmulType {
+  Divide
+  Multiply
+}
+
+struct VectorState {
+  Bits<7> sew;
+  VectorMultiplierDirection lmul_type;
+  Bits<2> log2_multiplier;
+}
+
+function vector_state {
+  returns VectorState
+  description {
+    Get the current vector state from CSRs
+  }
+  body {
+    VectorState state;
+
+    state.sew = 7'b1 << (3 + CSR[VTYPE].VSEW);
+    Bits<3> vlmul = CSR[VTYPE].VLMUL;
+    state.lmul_type = CSR[vtype].VLMUL[2] == 1'b1 ? VectorLmulType::Divide : VectorLmulType::Multiply;
+    state.log2_multiplier = CSR[vtype].VLMUL[1:0];
+    if (vlmul == 3'b101) {
+      state.log2_multiplier = 8;
+    } else if (vlmul == 3'b110) {
+      state.log2_multiplier = 4;
+    } else if (vlmul == 3'b111) {
+      state.log2_multiplier = 2;
+    }
+
+    return state;
+  }
+}