Add Smcsrind and Sscsrind CSR YAML Files

arch/csr/Smcsrind/mireg.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: mireg
+long_name: Machine Indirect Register Alias
+address: 0x351
+priv_mode: M
+length: MXLEN
+definedBy: Smcsrind
+description: |
+  The mireg machine indirect alias CSR is used to access another CSR's state
+  indirectly upon a read or write, as determined by the value of miselect.
+
+  The behavior upon accessing mireg from M-mode, while miselect holds a value
+  that is not implemented, is UNSPECIFIED.
+
+  [Note]
+  It is expected that implementations will typically raise an illegal instruction exception for
+  such accesses, so that, for example, they can be identified as software bugs. Platform
+  specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
+  behavior for such accesses.
+
+  Attempts to access mireg while miselect holds a number in an allocated and implemented range
+  results in a specific behavior that, for each combination of miselect and mireg, is defined by the
+  extension to which the miselect value is allocated.
+
+  [Note]
+  Ordinarily, mireg will access register state, access read-only 0 state, or raise an
+  illegal instruction exception.
+
+  [Note]
+  For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
+  recommended that the lower 32 bits of the register are accessed through mireg,
+  while the upper 32 bits are accessed through mireg4.
+fields:
+  VALUE:
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description: Register state of the CSR selected by the current `miselect` value
+    reset_value: UNDEFINED_LEGAL
+sw_read(): |

arch/csr/Smcsrind/mireg2.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: mireg2
+long_name: Machine Indirect Register Alias 2
+address: 0x352
+priv_mode: M
+length: MXLEN
+definedBy: Smcsrind
+description: |
+  The `mireg2` machine indirect alias CSR is used to access register state indirectly
+  upon a read or write, as determined by the value of `miselect`.
+
+  The behavior upon accessing `mireg2` from M-mode, while `miselect` holds a value
+  that is not implemented, is UNSPECIFIED.
+
+  [Note]
+    It is expected that implementations will typically raise an illegal instruction exception for
+    such accesses, so that, for example, they can be identified as software bugs. Platform
+    specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
+    behavior for such accesses.
+
+  Attempts to access `mireg2` while `miselect` holds a number in an allocated and implemented
+  range results in a specific behavior that, for each combination of `miselect` and `mireg2`, is
+  defined by the extension to which the `miselect` value is allocated.
+
+  [Note]
+    Ordinarily, `mireg2` will access register state, access read-only 0 state, or raise an
+    illegal instruction exception.
+
+  [Note]
+    For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
+    recommended that the lower 32 bits of the register are accessed through `mireg2`,
+    while the upper 32 bits are accessed through `mireg5`.
+
+fields:
+  VALUE:
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description: Register state of the CSR selected by the current `miselect` value
+    reset_value: UNDEFINED_LEGAL
+sw_read(): |

arch/csr/Smcsrind/mireg3.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: mireg3
+long_name: Machine Indirect Register Alias 3
+address: 0x353
+priv_mode: M
+length: MXLEN
+definedBy: Smcsrind
+description: |
+  The `mireg3` machine indirect alias CSR is used to access register state indirectly
+  upon a read or write, as determined by the value of `miselect`.
+
+  The behavior upon accessing `mireg3` from M-mode, while `miselect` holds a value
+  that is not implemented, is UNSPECIFIED.
+
+  [Note]
+    It is expected that implementations will typically raise an illegal instruction exception for
+    such accesses, so that, for example, they can be identified as software bugs. Platform
+    specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
+    behavior for such accesses.
+
+  Attempts to access `mireg3` while `miselect` holds a number in an allocated and implemented
+  range results in a specific behavior that, for each combination of `miselect` and `mireg3`, is
+  defined by the extension to which the `miselect` value is allocated.
+
+  [Note]
+    Ordinarily, `mireg3` will access register state, access read-only 0 state, or raise an
+    illegal instruction exception.
+
+  [Note]
+    For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
+    recommended that the lower 32 bits of the register are accessed through `mireg3`,
+    while the upper 32 bits are accessed through `mireg6`.
+
+fields:
+  VALUE:
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description: Register state of the CSR selected by the current `miselect` value
+    reset_value: UNDEFINED_LEGAL
+sw_read(): |

arch/csr/Smcsrind/mireg4.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: mireg4
+long_name: Machine Indirect Register Alias 4
+address: 0x355
+priv_mode: M
+length: MXLEN
+definedBy: Smcsrind
+description: |
+  The `mireg4` machine indirect alias CSR is used to access register state indirectly
+  upon a read or write, as determined by the value of `miselect`.
+
+  The behavior upon accessing `mireg4` from M-mode, while `miselect` holds a value
+  that is not implemented, is UNSPECIFIED.
+
+  [Note]
+    It is expected that implementations will typically raise an illegal instruction exception for
+    such accesses, so that, for example, they can be identified as software bugs. Platform
+    specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
+    behavior for such accesses.
+
+  Attempts to access `mireg4` while `miselect` holds a number in an allocated and implemented
+  range results in a specific behavior that, for each combination of `miselect` and `mireg4`, is
+  defined by the extension to which the `miselect` value is allocated.
+
+  [Note]
+    Ordinarily, `mireg4` will access register state, access read-only 0 state, or raise an
+    illegal instruction exception.
+
+  [Note]
+    For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
+    recommended that the upper 32 bits of the register are accessed through `mireg4`,
+    while the lower 32 bits are accessed through `mireg`, `mireg2`, or `mireg3`.
+
+fields:
+  VALUE:
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description: Register state of the CSR selected by the current `miselect` value
+    reset_value: UNDEFINED_LEGAL
+sw_read(): |

arch/csr/Smcsrind/mireg5.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: mireg5
+long_name: Machine Indirect Register Alias 5
+address: 0x356
+priv_mode: M
+length: MXLEN
+definedBy: Smcsrind
+description: |
+  The `mireg5` machine indirect alias CSR is used to access register state indirectly
+  upon a read or write, as determined by the value of `miselect`.
+
+  The behavior upon accessing `mireg5` from M-mode, while `miselect` holds a value
+  that is not implemented, is UNSPECIFIED.
+
+  [Note]
+    It is expected that implementations will typically raise an illegal instruction exception for
+    such accesses, so that, for example, they can be identified as software bugs. Platform
+    specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
+    behavior for such accesses.
+
+  Attempts to access `mireg5` while `miselect` holds a number in an allocated and implemented
+  range results in a specific behavior that, for each combination of `miselect` and `mireg5`, is
+  defined by the extension to which the `miselect` value is allocated.
+
+  [Note]
+    Ordinarily, `mireg5` will access register state, access read-only 0 state, or raise an
+    illegal instruction exception.
+
+  [Note]
+    For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
+    recommended that the upper 32 bits of the register are accessed through `mireg5`,
+    while the lower 32 bits are accessed through `mireg2`.
+
+fields:
+  VALUE:
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description: Register state of the CSR selected by the current `miselect` value
+    reset_value: UNDEFINED_LEGAL
+sw_read(): |

arch/csr/Smcsrind/mireg6.yaml

@@ -0,0 +1,43 @@
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: mireg6
+long_name: Machine Indirect Register Alias 6
+address: 0x357
+priv_mode: M
+length: MXLEN
+definedBy: Smcsrind
+description: |
+  The `mireg6` machine indirect alias CSR is used to access register state indirectly
+  upon a read or write, as determined by the value of `miselect`.
+
+  The behavior upon accessing `mireg6` from M-mode, while `miselect` holds a value
+  that is not implemented, is UNSPECIFIED.
+
+  [Note]
+    It is expected that implementations will typically raise an illegal instruction exception for
+    such accesses, so that, for example, they can be identified as software bugs. Platform
+    specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
+    behavior for such accesses.
+
+  Attempts to access `mireg6` while `miselect` holds a number in an allocated and implemented
+  range results in a specific behavior that, for each combination of `miselect` and `mireg6`, is
+  defined by the extension to which the `miselect` value is allocated.
+
+  [Note]
+    Ordinarily, `mireg6` will access register state, access read-only 0 state, or raise an
+    illegal instruction exception.
+
+  [Note]
+    For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
+    recommended that the upper 32 bits of the register are accessed through `mireg6`,
+    while the lower 32 bits are accessed through `mireg3`.
+
+fields:
+  VALUE:
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description: Register state of the CSR selected by the current `miselect` value
+    reset_value: UNDEFINED_LEGAL
+sw_read(): |

arch/csr/Smcsrind/miselect.yaml

@@ -0,0 +1,36 @@
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: miselect
+long_name: Machine Indirect Register Select
+address: 0x350
+priv_mode: M
+length: MXLEN
+definedBy: Smcsrind
+description: |
+  The CSRs listed in the table above provide a window for accessing register state indirectly. The value
+  of `miselect` determines which register is accessed upon read or write of each of the machine
+  indirect alias CSRs (`mireg*`). `miselect` value ranges are allocated to dependent extensions, which
+  specify the register state accessible via each `miregi` register, for each `miselect` value.
+  `miselect` is a WARL register.
+
+  The `miselect` register implements at least enough bits to support all implemented `miselect` values
+  (corresponding to the implemented extensions that utilize `miselect`/`mireg*` to indirectly access
+  register state). The `miselect` register may be read-only zero if there are no extensions implemented
+  that utilize it.
+
+  Values of `miselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for
+  custom use, presumably for accessing custom registers through the alias CSRs. Values of `miselect`
+  with the most-significant bit clear are designated only for standard use and are reserved until
+  allocated to a standard architecture extension. If XLEN is changed, the most-significant bit of
+  `miselect` moves to the new position, retaining its value from before.
+
+  An implementation is not required to support any custom values for `miselect`.
+fields:
+  Value:
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description: Selects which indirect register is accessed via `mireg*`.
+    reset_value: UNDEFINED_LEGAL
+sw_read(): |

arch/csr/Smcsrind/sireg.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: sireg
+long_name: Supervisor Indirect Register Alias
+address: 0x151
+priv_mode: S
+length: SXLEN
+definedBy: Sscsrind
+description: |
+  Access to `sireg` from M-mode or S-mode while `siselect` holds a number in a
+  standard-defined and implemented range results in specific behavior that, for each combination of
+  `siselect` and `sireg`, is defined by the extension to which the `siselect` value is allocated.
+
+  [Note]
+  Ordinarily, `sireg` will access register state, access read-only 0 state, or, unless
+  executing in a virtual machine (covered in the next section), raise an illegal instruction
+  exception.
+
+  Note that the widths of `siselect` and `sireg` are always the current XLEN rather than SXLEN. Hence,
+  for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current
+  privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code).
+
+  The behavior upon accessing `sireg` from M-mode or S-mode, while `siselect` holds a value that is
+  not implemented at supervisor level, is UNSPECIFIED.
+
+  [Note]
+  It is recommended that implementations raise an illegal instruction exception for such
+  accesses, to facilitate possible emulation (by M-mode) of these accesses.
+
+  [Note]
+  An extension is considered not to be implemented at supervisor level if machine level has
+  disabled the extension for S-mode, such as by the settings of certain fields in CSR
+  `menvcfg`, for example.
+
+fields:
+  VALUE:
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description: |
+      The data read from or written to the register selected by the current `siselect` value.
+    reset_value: UNDEFINED_LEGAL
+sw_read(): |

arch/csr/Smcsrind/sireg2.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: sireg2
+long_name: Supervisor Indirect Register Alias 2
+address: 0x152
+priv_mode: S
+length: SXLEN
+definedBy: Sscsrind
+description: |
+  Access to `sireg2` from M-mode or S-mode while `siselect` holds a number in a
+  standard-defined and implemented range results in specific behavior that, for each combination of
+  `siselect` and `sireg2`, is defined by the extension to which the `siselect` value is allocated.
+
+  [Note]
+  Ordinarily, `sireg2` will access register state, access read-only 0 state, or, unless
+  executing in a virtual machine (covered in the next section), raise an illegal instruction
+  exception.
+
+  Note that the widths of `siselect` and `sireg2` are always the current XLEN rather than SXLEN. Hence,
+  for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current
+  privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code).
+
+  The behavior upon accessing `sireg2` from M-mode or S-mode, while `siselect` holds a value that is
+  not implemented at supervisor level, is UNSPECIFIED.
+
+  [Note]
+  It is recommended that implementations raise an illegal instruction exception for such
+  accesses, to facilitate possible emulation (by M-mode) of these accesses.
+
+  [Note]
+  An extension is considered not to be implemented at supervisor level if machine level has
+  disabled the extension for S-mode, such as by the settings of certain fields in CSR
+  `menvcfg`, for example.
+
+fields:
+  VALUE:
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description: |
+      The data read from or written to the register selected by the current `siselect` value.
+    reset_value: UNDEFINED_LEGAL
+sw_read(): |