feat(idl): indirect csr support

arch/csr/Zihpm/hpmcounter10h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter10h
 long_name: User-mode Hardware Performance Counter 7, high half
 address: 0xC8A
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter10h`.
 

arch/csr/Zihpm/hpmcounter11h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter11h
 long_name: User-mode Hardware Performance Counter 8, high half
 address: 0xC8B
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter11h`.
 

arch/csr/Zihpm/hpmcounter12h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter12h
 long_name: User-mode Hardware Performance Counter 9, high half
 address: 0xC8C
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter12h`.
 

arch/csr/Zihpm/hpmcounter13h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter13h
 long_name: User-mode Hardware Performance Counter 10, high half
 address: 0xC8D
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter13h`.
 

arch/csr/Zihpm/hpmcounter14h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter14h
 long_name: User-mode Hardware Performance Counter 11, high half
 address: 0xC8E
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter14h`.
 

arch/csr/Zihpm/hpmcounter15h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter15h
 long_name: User-mode Hardware Performance Counter 12, high half
 address: 0xC8F
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter15h`.
 

arch/csr/Zihpm/hpmcounter16h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter16h
 long_name: User-mode Hardware Performance Counter 13, high half
 address: 0xC90
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter16h`.
 

arch/csr/Zihpm/hpmcounter17h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter17h
 long_name: User-mode Hardware Performance Counter 14, high half
 address: 0xC91
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter17h`.
 

arch/csr/Zihpm/hpmcounter18h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter18h
 long_name: User-mode Hardware Performance Counter 15, high half
 address: 0xC92
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter18h`.
 

arch/csr/Zihpm/hpmcounter19h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter19h
 long_name: User-mode Hardware Performance Counter 16, high half
 address: 0xC93
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter19h`.
 

arch/csr/Zihpm/hpmcounter20h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter20h
 long_name: User-mode Hardware Performance Counter 17, high half
 address: 0xC94
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter20h`.
 

arch/csr/Zihpm/hpmcounter21h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter21h
 long_name: User-mode Hardware Performance Counter 18, high half
 address: 0xC95
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter21h`.
 

arch/csr/Zihpm/hpmcounter22h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter22h
 long_name: User-mode Hardware Performance Counter 19, high half
 address: 0xC96
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter22h`.
 

arch/csr/Zihpm/hpmcounter23h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter23h
 long_name: User-mode Hardware Performance Counter 20, high half
 address: 0xC97
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter23h`.
 

arch/csr/Zihpm/hpmcounter24h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter24h
 long_name: User-mode Hardware Performance Counter 21, high half
 address: 0xC98
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter24h`.
 

arch/csr/Zihpm/hpmcounter25h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter25h
 long_name: User-mode Hardware Performance Counter 22, high half
 address: 0xC99
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter25h`.
 

arch/csr/Zihpm/hpmcounter26h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter26h
 long_name: User-mode Hardware Performance Counter 23, high half
 address: 0xC9A
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter26h`.
 

arch/csr/Zihpm/hpmcounter27h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter27h
 long_name: User-mode Hardware Performance Counter 24, high half
 address: 0xC9B
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter27h`.
 

arch/csr/Zihpm/hpmcounter28h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter28h
 long_name: User-mode Hardware Performance Counter 25, high half
 address: 0xC9C
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter28h`.
 

arch/csr/Zihpm/hpmcounter29h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter29h
 long_name: User-mode Hardware Performance Counter 26, high half
 address: 0xC9D
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter29h`.
 

arch/csr/Zihpm/hpmcounter30h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter30h
 long_name: User-mode Hardware Performance Counter 27, high half
 address: 0xC9E
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter30h`.
 

arch/csr/Zihpm/hpmcounter31h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter31h
 long_name: User-mode Hardware Performance Counter 28, high half
 address: 0xC9F
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter31h`.
 

arch/csr/Zihpm/hpmcounter3h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter3h
 long_name: User-mode Hardware Performance Counter 0, high half
 address: 0xC83
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter3h`.
 

arch/csr/Zihpm/hpmcounter4h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter4h
 long_name: User-mode Hardware Performance Counter 1, high half
 address: 0xC84
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter4h`.
 

arch/csr/Zihpm/hpmcounter5h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter5h
 long_name: User-mode Hardware Performance Counter 2, high half
 address: 0xC85
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter5h`.
 

arch/csr/Zihpm/hpmcounter6h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter6h
 long_name: User-mode Hardware Performance Counter 3, high half
 address: 0xC86
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter6h`.
 

arch/csr/Zihpm/hpmcounter7h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter7h
 long_name: User-mode Hardware Performance Counter 4, high half
 address: 0xC87
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter7h`.
 

arch/csr/Zihpm/hpmcounter8h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter8h
 long_name: User-mode Hardware Performance Counter 5, high half
 address: 0xC88
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter8h`.
 

arch/csr/Zihpm/hpmcounter9h.yaml

@@ -7,7 +7,6 @@ kind: csr
 name: hpmcounter9h
 long_name: User-mode Hardware Performance Counter 6, high half
 address: 0xC89
-base: 32
 description: |
   Alias for M-mode CSR `mhpmcounter9h`.
 

arch/inst/Zicsr/csrrc.yaml

@@ -24,16 +24,26 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  Csr csr_handle = direct_csr_lookup(csr);
+
   Boolean will_write = xs1 != 0;
-  check_csr(csr, will_write, $encoding);
 
-  XReg initial_csr_value = CSR[csr].sw_read();
+  # permission checks
+  if (csr_handle.valid == false) {
+    unimplemented_csr($encoding);
+  } else if (!compatible_mode?(csr_handle.mode, mode())) {
+    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+  } else if (will_write && csr_handle.writable == false) {
+    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+  }
+
+  XReg initial_csr_value = csr_sw_read(csr_handle);
 
   if (xs1 != 0) {
     # clear bits using the mask
     # performing any WARL transformations first
     XReg mask = X[xs1];
-    CSR[csr].sw_write(initial_csr_value & ~mask);
+    csr_sw_write(csr_handle, initial_csr_value & ~mask);
   }
 
   X[xd] = initial_csr_value;

arch/inst/Zicsr/csrrci.yaml

@@ -25,15 +25,25 @@ access:
 data_independent_timing: false
 operation(): |
   Boolean will_write = uimm != 0;
-  check_csr(csr, will_write, $encoding);
 
-  XReg initial_csr_value = CSR[csr].sw_read();
+  Csr csr_handle = direct_csr_lookup(csr);
 
-  if (uimm != 0) {
+  # permission checks
+  if (csr_handle.valid == false) {
+    unimplemented_csr($encoding);
+  } else if (!compatible_mode?(csr_handle.mode, mode())) {
+    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+  } else if (will_write && csr_handle.writable == false) {
+    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+  }
+
+  XReg initial_csr_value = csr_sw_read(csr_handle);
+
+  if (will_write) {
     # set bits using the mask
     # performing any WARL transformations first
     XReg mask = uimm;
-    CSR[csr].sw_write(initial_csr_value & ~mask);
+    csr_sw_write(csr_handle, initial_csr_value & ~mask);
   }
 
   X[xd] = initial_csr_value;

arch/inst/Zicsr/csrrs.yaml

@@ -31,15 +31,25 @@ access:
   vu: always
 operation(): |
   Boolean will_write = rs1 != 0;
-  check_csr(csr, will_write, $encoding);
 
-  XReg initial_csr_value = CSR[csr].sw_read();
+  Csr csr_handle = direct_csr_lookup(csr);
+
+  # permission checks
+  if (csr_handle.valid == false) {
+    unimplemented_csr($encoding);
+  } else if (!compatible_mode?(csr_handle.mode, mode())) {
+    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+  } else if (will_write && csr_handle.writable == false) {
+    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+  }
+
+  XReg initial_csr_value = csr_sw_read(csr_handle);
 
   if (will_write) {
     # set bits using the mask
     # performing any WARL transformations first
     XReg mask = X[rs1];
-    CSR[csr].sw_write(initial_csr_value | mask);
+    csr_sw_write(csr_handle, initial_csr_value | mask);
   }
 
   X[rd] = initial_csr_value;

arch/inst/Zicsr/csrrsi.yaml

@@ -25,15 +25,25 @@ access:
 data_independent_timing: false
 operation(): |
   Boolean will_write = uimm != 0;
-  check_csr(csr, will_write, $encoding);
 
-  XReg initial_csr_value = CSR[csr].sw_read();
+  Csr csr_handle = direct_csr_lookup(csr);
+
+  # permission checks
+  if (csr_handle.valid == false) {
+    unimplemented_csr($encoding);
+  } else if (!compatible_mode?(csr_handle.mode, mode())) {
+    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+  } else if (will_write && csr_handle.writable == false) {
+    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+  }
+
+  XReg initial_csr_value = csr_sw_read(csr_handle);
 
   if (will_write) {
     # set bits using the mask
     # performing any WARL transformations first
     XReg mask = uimm;
-    CSR[csr].sw_write(initial_csr_value | mask);
+    csr_sw_write(csr_handle, initial_csr_value | mask);
   }
 
   X[xd] = initial_csr_value;

arch/inst/Zicsr/csrrw.yaml

@@ -29,17 +29,26 @@ access:
   vs: always
   vu: always
 operation(): |
-  check_csr(csr, true, $encoding);
+  Csr csr_handle = direct_csr_lookup(csr);
 
   Bits<XLEN> initial_value = X[xs1];
 
+  # permission checks
+  if (csr_handle.valid == false) {
+    unimplemented_csr($encoding);
+  } else if (!compatible_mode?(csr_handle.mode, mode())) {
+    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+  } else if (csr_handle.writable == false) {
+    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+  }
+
   if (xd != 0) {
-    X[xd] = CSR[csr].sw_read();
+    X[xd] = csr_sw_read(csr_handle);
   }
 
   # writes the value in X[xs1] to the CSR,
   # performing any WARL transformations first
-  CSR[csr].sw_write(initial_value);
+  csr_sw_write(csr_handle, initial_value);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>