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read-only-zero case when CSR disabled - misa.yaml file #918

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read-only-zero case when CSR disabled - misa.yaml file #918

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b1a2a4d
read-only-zero when MISA_CSR_IMPLEMENTED=false
jevinjojo Jul 22, 2025
f857538
read-only-zero when MISA_CSR_IMPLEMENTED=false
jevinjojo Jul 22, 2025
a176914
guard CSR[misa] checks
jevinjojo Jul 28, 2025
7ae01d6
latest
jevinjojo Aug 2, 2025
15c0c7a
cleanup
jevinjojo Aug 10, 2025
1fbc3e7
indentations
jevinjojo Aug 16, 2025
37cf99a
Merge branch 'main' into misa-readonly-zero
jevinjojo Aug 16, 2025
4ede842
Merge branch 'main' into misa-readonly-zero
jevinjojo Aug 20, 2025
0bf0534
Merge branch 'main' into misa-readonly-zero
jevinjojo Sep 4, 2025
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103 changes: 72 additions & 31 deletions spec/std/isa/csr/misa.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -8,10 +8,14 @@ kind: csr
name: misa
long_name: Machine ISA Control
address: 0x301
# writable when misa CSR is implemented; read-only-0 otherwise
writable: true
priv_mode: M
length: MXLEN
description: Reports the XLEN and "major" extensions supported by the ISA.
description: |
Reports the XLEN and "major" extensions supported by the ISA.
[when,"MISA_CSR_IMPLEMENTED == false"]
This CSR is read-only-0 (all bits hardwired to zero) and cannot be written.
Comment on lines +16 to +18
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@dhower-qc dhower-qc Aug 20, 2025

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We've update how this is handled:

Suggested change
Reports the XLEN and "major" extensions supported by the ISA.
[when,"MISA_CSR_IMPLEMENTED == false"]
This CSR is read-only-0 (all bits hardwired to zero) and cannot be written.
- id: csr-misa-purpose
text: |
Reports the XLEN and "major" extensions supported by the ISA.
when:
param:
name: MISA_CSR_IMPLEMENTED
value: true
- id: csr-misa-unimplemented
text: |
This CSR is read-only-0 (all bits hardwired to zero) and cannot be written.
when:
param:
name: MISA_CSR_IMPLEMENTED
value: false

Note that the schema will reject this until #891 ships

definedBy: Sm
fields:
MXL:
Expand All @@ -20,7 +24,7 @@ fields:
description: XLEN in M-mode.
type: RO
reset_value(): |
return (MXLEN == 32) ? 2'b01 : 2'b10;
return (!MISA_CSR_IMPLEMENTED) ? 0 : (MXLEN == 32) ? 2'b01 : 2'b10;
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@dhower-qc dhower-qc Jul 22, 2025

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I would suggest either adding parenthesis or converting this to if (MISA_CSR_IMPLEMENTED) { .. } else { ... } for clarity.

(applies many times in this PR)

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@jevinjojo jevinjojo Jul 23, 2025

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should we also convert those existing ternary conditions to if-else blocks.

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@ThinkOpenly ThinkOpenly Jul 24, 2025

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should we also convert those existing ternary conditions to if-else blocks.

leave the existing ternaries, please.

A:
location: 0
description: |
Expand All @@ -29,9 +33,10 @@ fields:
[when,"MUTABLE_MISA_A == true"]
Writing 0 to this field will cause all atomic instructions to raise an `IllegalInstruction` exception.
type(): |
return (implemented?(ExtensionName::A) && MUTABLE_MISA_A) ? CsrFieldType::RW : CsrFieldType::RO;
return (!MISA_CSR_IMPLEMENTED) ? CsrFieldType::RO :
(implemented?(ExtensionName::A) && MUTABLE_MISA_A) ? CsrFieldType::RW : CsrFieldType::RO;
reset_value(): |
return implemented?(ExtensionName::A) ? 1 : 0;
return (!MISA_CSR_IMPLEMENTED) ? 0 : implemented?(ExtensionName::A) ? 1 : 0;
definedBy: A
B:
location: 1
Expand All @@ -41,9 +46,10 @@ fields:
[when,"MUTABLE_MISA_B == true"]
Writing 0 to this field will cause all bitmanip instructions to raise an `IllegalInstruction` exception.
type(): |
return (implemented?(ExtensionName::B) && MUTABLE_MISA_B) ? CsrFieldType::RW : CsrFieldType::RO;
return (!MISA_CSR_IMPLEMENTED) ? CsrFieldType::RO :
(implemented?(ExtensionName::B) && MUTABLE_MISA_B) ? CsrFieldType::RW : CsrFieldType::RO;
reset_value(): |
return implemented?(ExtensionName::B) ? 1 : 0;
return (!MISA_CSR_IMPLEMENTED) ? 0 : implemented?(ExtensionName::B) ? 1 : 0;
definedBy: B
C:
location: 2
Expand All @@ -54,9 +60,10 @@ fields:
Writing 0 to this field will cause all compressed instructions to raise an `IllegalInstruction` exception.
Additionally, IALIGN becomes 32.
type(): |
return (implemented?(ExtensionName::C) && MUTABLE_MISA_C) ? CsrFieldType::RW : CsrFieldType::RO;
return (!MISA_CSR_IMPLEMENTED) ? CsrFieldType::RO :
(implemented?(ExtensionName::C) && MUTABLE_MISA_C) ? CsrFieldType::RW : CsrFieldType::RO;
reset_value(): |
return implemented?(ExtensionName::C) ? 1 : 0;
return (!MISA_CSR_IMPLEMENTED) ? 0 : implemented?(ExtensionName::C) ? 1 : 0;
definedBy: C
D:
location: 3
Expand All @@ -70,9 +77,10 @@ fields:
Additionally, the upper 32-bits of the f registers will read as zero.
--
type(): |
return (implemented?(ExtensionName::D) && MUTABLE_MISA_D) ? CsrFieldType::RW : CsrFieldType::RO;
return (!MISA_CSR_IMPLEMENTED) ? CsrFieldType::RO :
(implemented?(ExtensionName::D) && MUTABLE_MISA_D) ? CsrFieldType::RW : CsrFieldType::RO;
reset_value(): |
return implemented?(ExtensionName::D) ? 1 : 0;
return (!MISA_CSR_IMPLEMENTED) ? 0 : implemented?(ExtensionName::D) ? 1 : 0;
definedBy: D
F:
location: 5
Expand All @@ -86,24 +94,34 @@ fields:
Writing 0 to this field with `misa.D` set will result in UNDEFINED behavior.
--
type(): |
return (implemented?(ExtensionName::F) && MUTABLE_MISA_F) ? CsrFieldType::RW : CsrFieldType::RO;
return (!MISA_CSR_IMPLEMENTED) ? CsrFieldType::RO :
(implemented?(ExtensionName::F) && MUTABLE_MISA_F) ? CsrFieldType::RW : CsrFieldType::RO;
reset_value(): |
return implemented?(ExtensionName::F) ? 1 : 0;
return (!MISA_CSR_IMPLEMENTED) ? 0 : implemented?(ExtensionName::F) ? 1 : 0;
definedBy: F
sw_write(csr_value): |
if (!MISA_CSR_IMPLEMENTED) {
return 0;
}
if (csr_value.F == 0 && csr_value.D == 1) {
return UNDEFINED_LEGAL_DETERMINISTIC;
}

# fall-through; write the intended value
return csr_value.F;
legal?(csr_value): |
if (!MISA_CSR_IMPLEMENTED) {
return true;
}
return !(csr_value.F == 0 && csr_value.D == 1);
G:
location: 6
description: |
Indicates support for all of the following extensions: `I`, `A`, `M`, `F`, `D`.
type(): |
if (!MISA_CSR_IMPLEMENTED) {
return CsrFieldType::RO;
}
if ((implemented?(ExtensionName::A) && MUTABLE_MISA_A) ||
(implemented?(ExtensionName::M) && MUTABLE_MISA_M) ||
(implemented?(ExtensionName::F) && MUTABLE_MISA_F) ||
Expand All @@ -113,6 +131,9 @@ fields:
return CsrFieldType::RO;
}
reset_value(): |
if (!MISA_CSR_IMPLEMENTED) {
return 0;
}
return (
implemented?(ExtensionName::A) &&
implemented?(ExtensionName::M) &&
Expand All @@ -126,17 +147,19 @@ fields:
[when,"MUTABLE_MISA_H == true"]
Writing 0 to this field will cause all attempts to enter VS- or VU- mode, execute a hypervisor instruction, or access a hypervisor CSR to raise an `IllegalInstruction` fault.
type(): |
return (implemented?(ExtensionName::H) && MUTABLE_MISA_H) ? CsrFieldType::RW : CsrFieldType::RO;
return (!MISA_CSR_IMPLEMENTED) ? CsrFieldType::RO :
(implemented?(ExtensionName::H) && MUTABLE_MISA_H) ? CsrFieldType::RW : CsrFieldType::RO;
definedBy: H
reset_value(): |
return implemented?(ExtensionName::H) ? 1 : 0;
return (!MISA_CSR_IMPLEMENTED) ? 0 : implemented?(ExtensionName::H) ? 1 : 0;
I:
location: 8
description: |
Indicates support for the `I` (base) extension.
type: RO
definedBy: I
reset_value: 1
reset_value(): |
return (!MISA_CSR_IMPLEMENTED) ? 0 : 1;
M:
location: 12
description: |
Expand All @@ -145,9 +168,10 @@ fields:
[when,"MUTABLE_MISA_M == true"]
Writing 0 to this field will cause all attempts to execute an integer multiply or divide instruction to raise an `IllegalInstruction` exception.
type(): |
return (implemented?(ExtensionName::M) && MUTABLE_MISA_M) ? CsrFieldType::RW : CsrFieldType::RO;
return (!MISA_CSR_IMPLEMENTED) ? CsrFieldType::RO :
(implemented?(ExtensionName::M) && MUTABLE_MISA_M) ? CsrFieldType::RW : CsrFieldType::RO;
reset_value(): |
return implemented?(ExtensionName::M) ? 1 : 0;
return (!MISA_CSR_IMPLEMENTED) ? 0 : implemented?(ExtensionName::M) ? 1 : 0;
definedBy: M
cert_normative_rules:
- id: csr_field.misa.M.disabled
Expand Down Expand Up @@ -182,17 +206,25 @@ fields:
Writing 0 to this field will cause all quad-precision floating point instructions to raise an `IllegalInstruction` exception.
--
type(): |
return MUTABLE_MISA_Q ? CsrFieldType::RW : CsrFieldType::RO;
reset_value: 1
return (!MISA_CSR_IMPLEMENTED) ? CsrFieldType::RO :
MUTABLE_MISA_Q ? CsrFieldType::RW : CsrFieldType::RO;
reset_value(): |
return (!MISA_CSR_IMPLEMENTED) ? 0 : 1;
definedBy: Q
sw_write(csr_value): |
if (!MISA_CSR_IMPLEMENTED) {
return 0;
}
if ((csr_value.F == 0 || csr_value.D == 0) && csr_value.Q == 1) {
return UNDEFINED_LEGAL_DETERMINISTIC;
}

# fall-through; write the intended value
return csr_value.Q;
legal?(csr_value): |
if (!MISA_CSR_IMPLEMENTED) {
return true;
}
return !(csr_value.Q == 1 && csr_value.D == 0);
S:
location: 18
Expand All @@ -202,9 +234,10 @@ fields:
[when,"MUTABLE_MISA_S == true"]
Writing 0 to this field will cause all attempts to enter S-mode or access S-mode state to raise an exception.
type(): |
return (implemented?(ExtensionName::S) && MUTABLE_MISA_S) ? CsrFieldType::RW : CsrFieldType::RO;
return (!MISA_CSR_IMPLEMENTED) ? CsrFieldType::RO :
(implemented?(ExtensionName::S) && MUTABLE_MISA_S) ? CsrFieldType::RW : CsrFieldType::RO;
reset_value(): |
return implemented?(ExtensionName::S) ? 1 : 0;
return (!MISA_CSR_IMPLEMENTED) ? 0 : implemented?(ExtensionName::S) ? 1 : 0;
definedBy: S
U:
location: 20
Expand All @@ -214,33 +247,41 @@ fields:
[when,"MUTABLE_MISA_U == true"]
Writing 0 to this field will cause all attempts to enter U-mode to raise an exception.
type(): |
return (implemented?(ExtensionName::U) && MUTABLE_MISA_U) ? CsrFieldType::RW : CsrFieldType::RO;
return (!MISA_CSR_IMPLEMENTED) ? CsrFieldType::RO :
(implemented?(ExtensionName::U) && MUTABLE_MISA_U) ? CsrFieldType::RW : CsrFieldType::RO;
reset_value(): |
return implemented?(ExtensionName::U) ? 1 : 0;
return (!MISA_CSR_IMPLEMENTED) ? 0 : implemented?(ExtensionName::U) ? 1 : 0;
definedBy: U
V:
location: 21
description: |
Indicates support for the `V` (vector) extension.

[when,"MUTABLE_MISA_V == true"]
[when,"MUTABLE_MISA_V == true && MISA_CSR_IMPLEMENTED == true"]
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@ThinkOpenly ThinkOpenly Aug 2, 2025

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I imagine we don't need this, since if any bits of the CSR are mutable, the CSR must be implemented. I'm not sure if we enforce that, though, which we should. To do that, we probably need some "EXTRA_VALIDATION" in Sm.yaml somewhere to check if any MUTABLE parameters are true when IMPLEMENTED is false. Is that something you want to include here, or shall we open a new issue?

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@jevinjojo jevinjojo Aug 4, 2025

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in the Sm.yaml file an extra_validation check under MISA_CSR_IMPLEMENTED and validation verifies that if any MISA bit (A-Z) is also need to marked as mutable. do we need to add error message if the condition violated

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in the Sm.yaml file an extra_validation check under MISA_CSR_IMPLEMENTED and validation verifies that if any MISA bit (A-Z) is also need to marked as mutable.

I'm leaning toward adding the extra_validation in the extensions where the mutability parameter is defined. For example, in spec/std/isa/ext/A.yaml, under MUTABLE_MISA_A add something like:

  extra_validation: assert MISA_CSR_IMPLEMENTED == true

(untested). In that way, "everybody" only needs to know that one "implemented" parameter, rather than Sm.yaml having to know every other "mutability" parameter.

do we need to add error message if the condition violated

No, that will come automatically when the architecture is resolved.

Writing 0 to this field will cause all attempts to execute a vector instruction to raise an `IllegalInstruction` trap.

[when,"MISA_CSR_IMPLEMENTED == false"]
This field reads as 0 and cannot be modified.
type(): |
return (implemented?(ExtensionName::V) && MUTABLE_MISA_V) ? CsrFieldType::RW : CsrFieldType::RO;
return (!MISA_CSR_IMPLEMENTED) ? CsrFieldType::RO :
(implemented?(ExtensionName::V) && MUTABLE_MISA_V) ? CsrFieldType::RW : CsrFieldType::RO;
reset_value(): |
return implemented?(ExtensionName::V) ? 1 : 0;
return (!MISA_CSR_IMPLEMENTED) ? 0 : implemented?(ExtensionName::V) ? 1 : 0;
definedBy: V
sw_read(): |
if (!MISA_CSR_IMPLEMENTED) {
return 0;
}
return (
(CSR[misa].MXL << (xlen() - 2)) |
(CSR[misa].V << 21) |
(CSR[misa].U << 20) |
(CSR[misa].S << 18) |
(CSR[misa].M << 12) |
(CSR[misa].I << 7) |
(CSR[misa].H << 6) |
((CSR[misa].A & CSR[misa].M & CSR[misa].F & CSR[misa].D) << 5) | # 'G'
(CSR[misa].F << 4) |
(CSR[misa].I << 8) |
(CSR[misa].H << 7) |
((CSR[misa].A & CSR[misa].M & CSR[misa].F & CSR[misa].D) << 6) | # 'G'
(CSR[misa].F << 5) |
(CSR[misa].D << 3) |
(CSR[misa].C << 2) |
(CSR[misa].B << 1) |
Expand All @@ -261,4 +302,4 @@ cert_test_procedures:
. Loop
.. Turn off each present bit invidually and try affected behaviors
. Check
.. Fail unless turning off bit disables extension as expected
.. Fail unless turning off bit disables extension as expected
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@dhower-qc dhower-qc Jul 22, 2025

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You'll need a newline at the end for regressions to pass

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