[ACT4] Interrupts Tests

[SadhviNarayanan]

Ports interrupt tests to new framework and adds InterruptsU.

[allenjbaum]

Why is the description of this PR "Provide a detailed description of the changes performed by the PR."

…

On Mon, Nov 17, 2025 at 11:07 AM SadhviNarayanan ***@***.***> wrote: Description Provide a detailed description of the changes performed by the PR. Related Issues Please list all the issues related to this PR. Use NA if no issues exist Ratified/Unratified Extensions - Ratified - Unratified List Extensions List the extensions that your PR affects. In case of unratified extensions, please provide a link to the spec draft that was referred to make this PR. Reference Model Used - SAIL - Spike - Other - < SPECIFY HERE > Mandatory Checklist: - All tests are compliant with the test-format spec present in this repo ? - Ran the new tests on RISCOF with SAIL/Spike as reference model successfully ? - Ran the new tests on RISCOF in coverage mode <https://riscof.readthedocs.io/en/stable/commands.html#coverage> - Link to Google-Drive folder containing the new coverage reports (See this <https://github.com/riscv-non-isa/riscv-arch-test/blob/main/CONTRIBUTION.md#uploading-test-stats> for more info): < SPECIFY HERE > Optional Checklist: - Were the tests hand-written/modified ? - Have you run these on any hard DUT model ? Please specify name and provide link if possible in the description - If you have modified arch_test.h Please provide a detailed description of the changes in the Description section above. ------------------------------ You can view, comment on, or merge this pull request online at: #745 Commit Summary - 21421f8 <21421f8> ExceptionsH coverpoints File Changes (2 files <https://github.com/riscv-non-isa/riscv-arch-test/pull/745/files> ) - *A* coverpoints/priv/ExceptionsH_coverage.svh <https://github.com/riscv-non-isa/riscv-arch-test/pull/745/files#diff-175d1ab4ef509555cf51e552c2c61868c29ddae45957754ec3fe5bca53fa8988> (887) - *A* coverpoints/priv/ExceptionsH_coverage_init.svh <https://github.com/riscv-non-isa/riscv-arch-test/pull/745/files#diff-f54bfabdbea65e95ac9bb0a8fe72b25d06b0b8819ea816355d94b04b75935d96> (11) Patch Links: - https://github.com/riscv-non-isa/riscv-arch-test/pull/745.patch - https://github.com/riscv-non-isa/riscv-arch-test/pull/745.diff — Reply to this email directly, view it on GitHub <#745>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AHPXVJXX5OM42XSXVRJGJMD35IMHZAVCNFSM6AAAAACML2IO7OVHI2DSMVQWIX3LMV43ASLTON2WKOZTGYZTINRVGY3TIOI> . You are receiving this because you are subscribed to this thread.Message ID: ***@***.***>

[davidharrishmc]

@SadhviNarayanan this is a massive PR. Excellent material. It took a long time to review carefully.

I have not reviewed the Interrupts code, but presume it is the same as before but fixed to compile.

[davidharrishmc]

Reviewed through cp_user_mti. Apply these comments to the later coverpoints, and try running the tests, and then let me know when they are all ready to review.

[davidharrishmc]

model_test may have a conflict with the act4 branch. Check if you really want to be changing it.

I don't think this will compile until you have the v bit in the RVVI interface.
When it compiles and has no merge conflicts, it's ready to merge.

[davidharrishmc]

test

[davidharrishmc]

mode_virt isn't defined. Can you add a v bit to the instruction data structure, similar to ins.prev.mode?

[davidharrishmc]

how does this differ from the "modes" coverpoint and why does V=? in M_mode (rather than 0)?

[davidharrishmc]

One or two possible bugs and some comments on style. I know you inherited sloppy Interrupt code. Looking good. Does it run and are you getting some coverage?

[davidharrishmc]

This could be a csrrci to be consistent with 419.