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(ACT4) Converted Virtual Memory tests to ACT4 framework #908

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273f0aa
Converted Sv39 tests
Zain2050 Feb 4, 2026
1d756fa
Converted Sv48 tests
Zain2050 Feb 4, 2026
79aded8
Converted Sv57 tests
Zain2050 Feb 4, 2026
985a16f
Converted Sv32 tests
Zain2050 Feb 4, 2026
2a0a5d9
Removed Sv folder
Zain2050 Feb 4, 2026
4ef1821
Adjusted PTE macros
Zain2050 Feb 4, 2026
b233965
Enable Sv57 in cvw-rv64gc/sail.json
Zain2050 Feb 4, 2026
ad35127
Added XLEN param to Bare mode tests
Zain2050 Feb 6, 2026
9342d8a
Merge branch 'act4' into Sv_ACT4
Zain2050 Feb 15, 2026
d1ea785
Move Sv32,39,48,57 folders into a single Sv folder
Zain2050 Feb 15, 2026
45896e5
Correct grain value for cvw sail.json file
Zain2050 Feb 15, 2026
5fc2c07
Converted Sv_pmp tests
Zain2050 Feb 15, 2026
bf26060
Add PMP shift macros
Zain2050 Feb 15, 2026
f33889a
Moved Svade tests into a separate folder
Zain2050 Feb 18, 2026
b97f320
Merge branch 'act4' of https://github.com/riscv-non-isa/riscv-arch-te…
Zain2050 Feb 18, 2026
a9dea07
Merge branch 'act4' into Sv_ACT4
UmerShahidengr Feb 18, 2026
2369199
Clear menvcfg.ADUE for Svade tests
Zain2050 Feb 19, 2026
eecc2a4
Remove duplicate macro
Zain2050 Feb 19, 2026
11f393c
Merge branch 'act4' into Sv_ACT4
Zain2050 Feb 19, 2026
4840efb
Removed SKIP_MTVAL flag from the tests
Zain2050 Feb 20, 2026
77f6494
Merge branch 'act4' into Sv_ACT4
Zain2050 Feb 20, 2026
e6486c5
Merge branch 'act4' into Sv_ACT4
UmerShahidengr Feb 23, 2026
3796fcd
Merge branch 'act4' into Sv_ACT4
UmerShahidengr Feb 23, 2026
bf5ef17
Add Mmode definition to arch_test.h
UmerShahidengr Feb 23, 2026
a6f9afd
Merge branch 'act4' into Sv_ACT4
UmerShahidengr Feb 23, 2026
46b02c8
Merge branch 'act4' into Sv_ACT4
UmerShahidengr Feb 23, 2026
d12ce2c
Add NORUN to SBE tests
Zain2050 Feb 25, 2026
5257961
Add NORUN to Svnapot_not_supported tests
Zain2050 Feb 25, 2026
a6b1948
Disable Svrsw60t59b from spike64max json
Zain2050 Feb 25, 2026
21c65b4
Fix for clang in test_macros.h
Zain2050 Feb 25, 2026
cd0fd1b
Enclose hgatp read within ifdef htrap_routine
Zain2050 Feb 25, 2026
ae85557
Merge branch 'act4' into Sv_ACT4
Zain2050 Feb 25, 2026
86817d1
Merge branch 'act4' into Sv_ACT4
UmerShahidengr Feb 26, 2026
86692aa
Merge branch 'act4' into Sv_ACT4
UmerShahidengr Feb 27, 2026
4be73ea
Merge branch 'act4' into Sv_ACT4
Zain2050 Feb 28, 2026
c4cbc4f
Updated Sv according to new SIGUPD macro
Zain2050 Mar 1, 2026
72f3f39
Updated Svade & Sv_pmp according to new SIGUPD macro
Zain2050 Mar 1, 2026
67545b0
Merge branch 'act4' into Sv_ACT4
Zain2050 Mar 1, 2026
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2 changes: 1 addition & 1 deletion config/spike/spike-rv64-max/sail.json
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Original file line number Diff line number Diff line change
Expand Up @@ -434,7 +434,7 @@
"supported": true
},
"Svrsw60t59b": {
"supported": true
"supported": false
},
"Smcntrpmf": {
"supported": true
Expand Down
6 changes: 5 additions & 1 deletion tests/env/arch_test.h
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Original file line number Diff line number Diff line change
Expand Up @@ -745,6 +745,7 @@
#define HSmode 0x9
#define VSmode 0x5
#define VUmode 0x4
#define Mmode 0x3
#define Smode 0x1
#define Umode 0x0

Expand Down Expand Up @@ -1390,11 +1391,14 @@ common_\__MODE__\()excpt_handler:

// extract and test satp.MODE from trapping mode; if !=bare, VA, skip reloc
csrr T2, CSR_SATP
#ifdef rvtest_htrap_routine
csrr T6, CSR_MISA // select effective xATP based on misa[7] (H)
slli T6, T6, XLEN-7-1
bgez T6, 1f // keep SATP if no hypervisor
csrr T2, CSR_HGATP // substitute HGATP if hypervisor
1: srli T2, T2, MODE_LSB
1:
#endif
srli T2, T2, MODE_LSB
addi T4, sp, 1*sv_area_sz // T4 points to HS/S mode sv_area
bnez T2, sv_\__MODE__\()epc // skip reloc if not bare mode

Expand Down
127 changes: 79 additions & 48 deletions tests/env/test_macros.h
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Original file line number Diff line number Diff line change
Expand Up @@ -28,13 +28,6 @@
#define VMEM vmem_bgn_off


#define SATP_SETUP(_TR0, _TR1, MODE);\
LA(_TR0, rvtest_Sroot_pg_tbl) ;\
LI(_TR1, MODE) ;\
srli _TR0, _TR0, 12 ;\
or _TR0, _TR0, _TR1 ;\
csrw satp, _TR0 ;\

//****NOTE: label `rvtest_Sroot_pg_tbl` must be declared after RVTEST_DATA_END
// in the test aligned at 4kiB (use .align 12)
#define PTE_SETUP_COMMON(_PAR, _PR, _TR0, _TR1, _VAR, level) ;\
Expand All @@ -50,30 +43,6 @@
or _PAR, _PAR, _PR ;\
SREG _PAR, 0(_TR1);

#define PTE_SETUP_RV32(_PAR, _PR, _TR0, _TR1, VA, level) ;\
srli _PAR, _PAR, 12 ;\
slli _PAR, _PAR, 10 ;\
or _PAR, _PAR, _PR ;\
.if (level==1) ;\
LA(_TR1, rvtest_Sroot_pg_tbl) ;\
LI(_TR0, ((VA>>22)&0x3FF)<<2) ;\
.endif ;\
.if (level==0) ;\
LA(_TR1, rvtest_slvl1_pg_tbl) ;\
LI(_TR0, ((VA>>12)&0x3FF)<<2) ;\
.endif ;\
add _TR1, _TR1, _TR0 ;\
SREG _PAR, 0(_TR1);

// More Robust version of PTE_SETUP_32 to setup a PTE for a PA using Va
// in a single line.
//args: PA: Label of Physical Address, PERMS: permissions in hex
//args: VA: Virtual Address in hex, level: Level to store at
#define PTE_SETUP_RV32_New(PA_LBL, PERMS, VA, level) ;\
LA(a0, PA_LBL) ;\
LI(a1, PERMS) ;\
PTE_SETUP_RV32(a0, a1, t0, t1, VA, level) ;\

// Appends 12-bit page offset from PA to VA, and stores it
// to S save area; a0 must point to M save area
#define SAVE_AREA_SETUP(VA, PA_LBL, _REG_NAME) ;\
Expand All @@ -100,6 +69,21 @@
SREG t2, _REG_NAME##_bgn_off+1*sv_area_sz(a0) ;\
addi a0, a0, -2*sv_area_sz ;

#define PTE_SETUP_RV32(_PAR, _PR, _TR0, _TR1, VA, level) ;\
srli _PAR, _PAR, 12 ;\
slli _PAR, _PAR, 10 ;\
or _PAR, _PAR, _PR ;\
.if (level==1) ;\
LA(_TR1, rvtest_Sroot_pg_tbl) ;\
LI(_TR0, ((VA>>22)&0x3FF)<<2) ;\
.endif ;\
.if (level==0) ;\
LA(_TR1, rvtest_slvl0_pg_tbl) ;\
LI(_TR0, ((VA>>12)&0x3FF)<<2) ;\
.endif ;\
add _TR1, _TR1, _TR0 ;\
SREG _PAR, 0(_TR1) ;

#define PTE_SETUP_RV64(_PAR, _PR, _TR0, _TR1, VA, level, mode) ;\
srli _PAR, _PAR, 12 ;\
slli _PAR, _PAR, 10 ;\
Expand All @@ -114,7 +98,7 @@
.set vpn, ((VA >> 21) & 0x1FF) << 3 ;\
.endif ;\
.if (level == 0) ;\
LA(_TR1, rvtest_slvl2_pg_tbl) ;\
LA(_TR1, rvtest_slvl0_pg_tbl) ;\
.set vpn, ((VA >> 12) & 0x1FF) << 3 ;\
.endif ;\
.endif ;\
Expand All @@ -124,15 +108,15 @@
.set vpn, ((VA >> 39) & 0x1FF) << 3 ;\
.endif ;\
.if (level == 2) ;\
LA(_TR1, rvtest_slvl1_pg_tbl) ;\
LA(_TR1, rvtest_slvl2_pg_tbl) ;\
.set vpn, ((VA >> 30) & 0x1FF) << 3 ;\
.endif ;\
.if (level == 1) ;\
LA(_TR1, rvtest_slvl2_pg_tbl) ;\
LA(_TR1, rvtest_slvl1_pg_tbl) ;\
.set vpn, ((VA >> 21) & 0x1FF) << 3 ;\
.endif ;\
.if (level == 0) ;\
LA(_TR1, rvtest_slvl3_pg_tbl) ;\
LA(_TR1, rvtest_slvl0_pg_tbl) ;\
.set vpn, ((VA >> 12) & 0x1FF) << 3 ;\
.endif ;\
.endif ;\
Expand All @@ -142,26 +126,77 @@
.set vpn, ((VA >> 48) & 0x1FF) << 3 ;\
.endif ;\
.if (level == 3) ;\
LA(_TR1, rvtest_slvl1_pg_tbl) ;\
LA(_TR1, rvtest_slvl3_pg_tbl) ;\
.set vpn, ((VA >> 39) & 0x1FF) << 3 ;\
.endif ;\
.if (level == 2) ;\
LA(_TR1, rvtest_slvl2_pg_tbl) ;\
.set vpn, ((VA >> 30) & 0x1FF) << 3 ;\
.endif ;\
.if (level == 1) ;\
LA(_TR1, rvtest_slvl3_pg_tbl) ;\
LA(_TR1, rvtest_slvl1_pg_tbl) ;\
.set vpn, ((VA >> 21) & 0x1FF) << 3 ;\
.endif ;\
.if (level == 0) ;\
LA(_TR1, rvtest_slvl3_pg_tbl) ;\
LA(_TR1, rvtest_slvl0_pg_tbl) ;\
.set vpn, ((VA >> 12) & 0x1FF) << 3 ;\
.endif ;\
.endif ;\
LI(_TR0, vpn) ;\
add _TR1, _TR1, _TR0 ;\
SREG _PAR, 0(_TR1) ;

#define PTE_SETUP_SV32(PA_LBL, PERMS, VA, level) ;\
LA(a0, PA_LBL) ;\
LI(a1, PERMS) ;\
PTE_SETUP_RV32(a0, a1, t0, t1, VA, level) ;

#define SUPERPAGE_PTE_SETUP_SV32(PA_LBL, PERMS, VA, level) ;\
LA(a0, (PA_LBL)) ;\
srli a0, a0, 22 ;\
slli a0, a0, 22 ;\
LI(a1, PERMS) ;\
PTE_SETUP_RV32(a0, a1, t0, t1, VA, level) ;

#define PTE_SETUP_SV39(PA_LBL, PERMS, VA, level) ;\
LA(a0, PA_LBL) ;\
LI(a1, PERMS) ;\
PTE_SETUP_RV64(a0, a1, t0, t1, VA, level, sv39) ;

#define SUPERPAGE_PTE_SETUP_SV39(PA_LBL, PERMS, VA, level) ;\
.set PA_SHIFT, (level*9)+12 ;\
LA(a0, (PA_LBL)) ;\
srli a0, a0, PA_SHIFT ;\
slli a0, a0, PA_SHIFT ;\
LI(a1, PERMS) ;\
PTE_SETUP_RV64(a0, a1, t0, t1, VA, level, sv39) ;

#define PTE_SETUP_SV48(PA_LBL, PERMS, VA, level) ;\
LA(a0, PA_LBL) ;\
LI(a1, PERMS) ;\
PTE_SETUP_RV64(a0, a1, t0, t1, VA, level, sv48) ;

#define SUPERPAGE_PTE_SETUP_SV48(PA_LBL, PERMS, VA, level) ;\
.set PA_SHIFT, (level*9)+12 ;\
LA(a0, (PA_LBL)) ;\
srli a0, a0, PA_SHIFT ;\
slli a0, a0, PA_SHIFT ;\
LI(a1, PERMS) ;\
PTE_SETUP_RV64(a0, a1, t0, t1, VA, level, sv48) ;

#define PTE_SETUP_SV57(PA_LBL, PERMS, VA, level) ;\
LA(a0, PA_LBL) ;\
LI(a1, PERMS) ;\
PTE_SETUP_RV64(a0, a1, t0, t1, VA, level, sv57) ;

#define SUPERPAGE_PTE_SETUP_SV57(PA_LBL, PERMS, VA, level) ;\
.set PA_SHIFT, (level*9)+12 ;\
LA(a0, (PA_LBL)) ;\
srli a0, a0, PA_SHIFT ;\
slli a0, a0, PA_SHIFT ;\
LI(a1, PERMS) ;\
PTE_SETUP_RV64(a0, a1, t0, t1, VA, level, sv57) ;

#define PTE_PERMUPD_RV32(_PR, _TR0, _TR1, VA, level) ;\
.if (level==1) ;\
LA(_TR1, rvtest_Sroot_pg_tbl) ;\
Expand All @@ -179,13 +214,12 @@
or _TR0, _TR0, _PR ;\
SREG _TR0, 0(_TR1) ;


#define SATP_SETUP_SV32 ;\
LA(t6, rvtest_Sroot_pg_tbl) ;\
LI(t5, SATP32_MODE) ;\
srli t6, t6, 12 ;\
or t6, t6, t5 ;\
csrw satp, t6 ;
#define SATP_SETUP_SV32 ;\
LA(t6, rvtest_Sroot_pg_tbl) ;\
LI(t5, SATP32_MODE) ;\
srli t6, t6, 12 ;\
or t6, t6, t5 ;\
csrw satp, t6 ;

#define SATP_SETUP_RV64(MODE) ;\
LA(t6, rvtest_Sroot_pg_tbl) ;\
Expand All @@ -198,9 +232,6 @@
.if (MODE == sv57) ;\
LI(t5, (SATP64_MODE) & (SATP_MODE_SV57 << 60)) ;\
.endif ;\
.if (MODE == sv64) ;\
LI(t5, (SATP64_MODE) & (SATP_MODE_SV64 << 60)) ;\
.endif ;\
srli t6, t6, 12 ;\
or t6, t6, t5 ;\
csrw satp, t6 ;
9 changes: 9 additions & 0 deletions tests/env/utils.h
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Original file line number Diff line number Diff line change
Expand Up @@ -89,6 +89,15 @@
#define RVTEST_WORD_PTR .word
#endif

// PMP macros
#define PMP0_CFG_SHIFT 0
#define PMP1_CFG_SHIFT 8
#define PMP2_CFG_SHIFT 16
#define PMP3_CFG_SHIFT 24
#define PMP4_CFG_SHIFT 32
#define PMP5_CFG_SHIFT 40
#define PMP6_CFG_SHIFT 48
#define PMP7_CFG_SHIFT 56

// RVTEST_TESTDATA_LOAD_INT(data_ptr, dest_reg) loads an integer value from the
// test data section into dest_reg and increments the data_ptr pointer by SIG_STRIDE.
Expand Down
133 changes: 133 additions & 0 deletions tests/priv/Sv/Sv32/mprv_vm_bare_mode.S
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@@ -0,0 +1,133 @@
// --------------------------------------------------------------------------------------------------------------------------------
// Test cases are as follows:
// --------------------------------------------------------------------------------------------------------------------------------
// 1. mstatus.MPRV set, mstatus.MPP = S-mode and virtualization is not enabled (Bare Mode):
// Then, in M-Mode, Load, Store & Execute is performed --> required: No Fault
// 2. mstatus.MPRV set, mstatus.MPP = U-mode and virtualization is not enabled (Bare Mode):
// Then, in M-Mode, Load, Store & Execute is performed --> required: No Fault
//
// Total Expected Faults :: 0
//---------------------------------------------------------------------------------------------------------------------------------

##### START_TEST_CONFIG #####
# REQUIRED_EXTENSIONS: [I, S]
# params:
# MXLEN: 32
# MARCH: rv32i_zicsr
# CONFIG_DEPENDENT: true
##### END_TEST_CONFIG #####

#define TEST_FILE "vm_mprv_satp_bare_mode.S"
#define SIGUPD_COUNT 15
#define rvtest_mtrap_routine
#define rvtest_strap_routine
#define RVTEST_PRIV_TEST
#define SKIP_MEPC

#include "riscv_arch_test.h"

RVTEST_BEGIN

//---------------------------------------------------------------------------------------------------------------------------------
// Test RWX permissions
.macro VERIFICATION_RWX TEST_CASE
// As we are in bare mode, we will test using physical address
LA( a5, rvtest_data_1)
addi a2, a2, 16

// Test store permission
\TEST_CASE\()_store:
sw a2, 20(a5)
nop

// Test load permission
\TEST_CASE\()_load:
lw a3, 20(a5)
nop

// Test execute permission
LI( x4, 0xACCE) // Store a value which is to be checked in trap handler
\TEST_CASE\()_exec:
jalr ra, a5, 0
nop

// Signature Update
RVTEST_SIGUPD(x2, x5, x4, a2, \TEST_CASE\()_store, \TEST_CASE\()_store_str)
RVTEST_SIGUPD(x2, x5, x4, a3, \TEST_CASE\()_load, \TEST_CASE\()_load_str)
RVTEST_SIGUPD(x2, x5, x4, a4, \TEST_CASE\()_exec, \TEST_CASE\()_exec_str)
.endm


main:
li a2, 0x800 // Test signature initialization

//---------------------------------------------------------------------------------------------------------------------------------
// Test case 1: Set mstatus.MPRV and set mstatus.MPP to S Mode
//---------------------------------------------------------------------------------------------------------------------------------

LI( t0, MSTATUS_MPRV)
CSRS( mstatus, t0)
LI( t0, 0x1800)
CSRC( mstatus, t0)
LI( t0, 0x800)
CSRS( mstatus, t0) // Set to Smode

test1_mstatus:
RVTEST_SIGUPD_CSR_READ(mstatus, a4, test1_mstatus, test1_mstatus_str)

// Verify Load, Store & Execute in Bare mode
VERIFICATION_RWX test1

RVTEST_GOTO_MMODE

//---------------------------------------------------------------------------------------------------------------------------------
// Test case 2: Set mstatus.MPRV and set mstatus.MPP to U Mode
//---------------------------------------------------------------------------------------------------------------------------------

LI( s7, MSTATUS_MPRV)
CSRS( mstatus, s7)
LI( s7, 0x1800)
CSRC( mstatus, s7) // Set to Umode

test2_mstatus:
RVTEST_SIGUPD_CSR_READ(mstatus, a4, test2_mstatus, test2_mstatus_str)

// Verify Load, Store & Execute in Bare mode
VERIFICATION_RWX test2

RVTEST_GOTO_MMODE


//---------------------------------------------------------------------------------------------------------------------------------
RVTEST_CODE_END
RVTEST_DATA_BEGIN

//---------------------------------------------------------------------------------------------------------------------------------
// PHYSICAL ADDRESS REGION FOR TESTING
//---------------------------------------------------------------------------------------------------------------------------------
.align 12
rvtest_data_1:
nop
addi a4, a2, 4
jr ra
nop
.word 0xbeefcaf1 // Random word
.word 0xbeefcaf2 // Random word
nop
jr ra

//---------------------------------------------------------------------------------------------------------------------------------


canary_mismatch: .string "Testcase signature canary mismatch!"
test1_mstatus_str: .string "\"Mismatch in mstatus value in Test Case 1!\""
test1_store_str: .string "\"Mismatch during sw in Test Case 1!\""
test1_load_str: .string "\"Mismatch during lw in Test Case 1!\""
test1_exec_str: .string "\"Mismatch during jalr in Test Case 1!\""
test2_mstatus_str: .string "\"Mismatch in mstatus value in Test Case 2!\""
test2_store_str: .string "\"Mismatch during sw in Test Case 2!\""
test2_load_str: .string "\"Mismatch during lw in Test Case 2!\""
test2_exec_str: .string "\"Mismatch during jalr in Test Case 2!\""

RVTEST_DATA_END
RVTEST_SIG_SETUP
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