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chihminchao wants to merge 2 commits into from
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Exclude svnapot svpbmt #919

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972ae00
tests: vm: exclude reserved_Svnapot testcases
chihminchao Feb 10, 2026
50f5207
tests: vm: exclude reserved_Svpbmt testcases
chihminchao Feb 10, 2026
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2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_svnapot_S_mode.S
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",add_feature)
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); check ISA:=regex(^((?!Svnapot).)*$); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",add_feature)

RVTEST_SIGBASE( x13,signature_x13_1)
# ---------------------------------------------------------------------------------------------
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2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_svpbmt_S_mode.S
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Original file line number Diff line number Diff line change
Expand Up @@ -55,7 +55,7 @@ starting_point:
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",add_feature)
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); check ISA:=regex(^((?!Svpbmt).)*$); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",add_feature)

RVTEST_SIGBASE( x13,signature_x13_1)
# ---------------------------------------------------------------------------------------------
Expand Down
2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/vm_sv48/src/sv48_reserved_svnapot_S_mode.S
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True", sv48_tests)
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); check ISA:=regex(^((?!Svnapot).)*$); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True", sv48_tests)

RVTEST_SIGBASE( x13,signature_x13_1)
# ---------------------------------------------------------------------------------------------
Expand Down
2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/vm_sv48/src/sv48_reserved_svpbmt_S_mode.S
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Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,7 @@ starting_point:
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True", sv48_tests)
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); check ISA:=regex(^((?!Svpbmt).)*$); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True", sv48_tests)

RVTEST_SIGBASE( x13,signature_x13_1)
# ---------------------------------------------------------------------------------------------
Expand Down
2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/vm_sv57/src/sv57_reserved_svnapot_S_mode.S
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True", sv57_tests)
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); check ISA:=regex(^((?!Svnapot).)*$); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True", sv57_tests)

RVTEST_SIGBASE( x13,signature_x13_1)
# ---------------------------------------------------------------------------------------------
Expand Down
2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/vm_sv57/src/sv57_reserved_svpbmt_S_mode.S
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,7 @@ starting_point:
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True", sv57_tests)
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); check ISA:=regex(^((?!Svpbmt).)*$); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True", sv57_tests)

RVTEST_SIGBASE( x13,signature_x13_1)
# ---------------------------------------------------------------------------------------------
Expand Down