Merge pull request #917 from riscv/tm_reg

Refer to "trigger registers" as "Trigger Module Registers"

Author: timsifive

Sdtrig.tex

@@ -337,7 +337,7 @@ \section{Multiple State Change Instructions} \label{sec:multistate}
 executing it again leaves the hart in a state closely resembling the state it
 would have been in if the instruction had only been executed once.
 
-\section{Trigger Registers}
+\section{Trigger Module Registers}
 
 These registers are CSRs, accessible using the RISC-V {\tt csr} opcodes and
 optionally also using abstract debug commands.
@@ -373,7 +373,7 @@ \section{Trigger Registers}
 This avoids the problem of a partially written trigger firing at a different
 time than is expected.
 
-Attempts to access an unimplemented Trigger Register raise an illegal instruction
-exception.
+Attempts to access an unimplemented Trigger Module Register raise an illegal
+instruction exception.
 
 \input{hwbp_registers.tex}

introduction.tex

@@ -171,7 +171,7 @@ \subsubsection{Minor Changes from 0.13 to 1.0}
     \item \FcsrDcsrStopcount only applies to hart-local counters. \PR{405}
     \item \FdmDmstatusVersion may be invalid when \FdmDmcontrolDmactive=0. \PR{414}
     \item Address triggers (\RcsrMcontrol) may fire on any accessed address. \PR{421}
-    \item All trigger registers (Section~\ref{csrTrigger}) are optional. \PR{431}
+    \item All Trigger Module registers (Section~\ref{csrTrigger}) are optional. \PR{431}
     \item When extending IR, \RdtmBypass still is all ones. \PR{437}
     \item \FcsrDcsrEbreaks and \FcsrDcsrEbreaku are WARL. \PR{458}
     \item NMIs are disabled by \FcsrDcsrStepie. \PR{465}

xml/hwbp_registers.xml

@@ -1,5 +1,5 @@
-<registers name="Trigger Registers" prefix="CSR_" label="trigger">
-    The trigger registers, except \RcsrMscontext, \RcsrScontext, and \RcsrHcontext, are only accessible in machine
+<registers name="Trigger Module Registers" prefix="CSR_" label="trigger">
+    The Trigger Module registers, except \RcsrMscontext, \RcsrScontext, and \RcsrHcontext, are only accessible in machine
     and Debug Mode to prevent untrusted user code from causing entry into Debug
     Mode without the OS's permission.
 
@@ -16,7 +16,7 @@
 
     <register name="Trigger Select" short="tselect" address="0x7a0">
         This register determines which trigger is accessible through the other
-        trigger registers. It is optional if no triggers are implemented.  The
+        Trigger Module registers. It is optional if no triggers are implemented.  The
         set of accessible triggers must start at 0, and be contiguous.
 
         This register is \warl.