doc: update rz-asm manual with formatting improvements and environment variables

.github/workflows/linter.yml

@@ -166,3 +166,21 @@ jobs:
       uses: actions/checkout@v6
     - name: REUSE Compliance Check
       uses: fsfe/reuse-action@v6
+
+  rizin-format:
+    needs: changes
+    runs-on: ubuntu-24.04
+    if: ${{ needs.changes.outputs.clang-format == 'true' }}
+    steps:
+      - name: Checkout repository
+        uses: actions/checkout@v6
+
+      - name: Install clang-format-20 and gitpython
+        run: |
+          sudo apt --assume-yes install clang-format-20
+          sudo pip install gitpython --break-system-packages
+
+      - name: Run Rizin Format Script
+        run: |
+          python3 sys/clang-format.py
+          git diff --exit-code

binrz/man/rizin.1

@@ -121,50 +121,45 @@ Same as -e bin.usextr=false, do not use extract plugins, useful for dyldcache
 Do not load strings or load them even in raw
 .El
 .Sh ENVIRONMENT
-.Bl -tag -width RZ_DYLDCACHE_FILTER
-.It Ev ANSICON
-W & H of the buffer and w & h of the window in the form of: "WxH (wxh)"
-.It Ev DEBUGINFOD_URLS
-Use alternative debuginfod server via bin.dbginfo.debuginfod_urls
-.It Ev COLUMNS
-Terminal columns to use
-.It Ev RZ_ABORTLEVEL
-Target log level/severity when to abort
-(0:DEBUG, 1:VERBOSE, 2:INFO, 3:WARN, 4:ERROR, 5:FATAL)
-.It Ev RZ_CURL
-Whether to use curl (for SSL support)
-.It Ev RZ_DEBUG_ASSERT
-Set a breakpoint when hitting an assert
-.It Ev RZ_DEBUG_TOOL
-Debug tool to use when showing error messages and crash signal
-.It Ev RZ_DYLDCACHE_FILTER
-dyld cache filter (MacOS dynamic libraries location(s) at runtime)
-.It Ev RZ_HTTP_AUTHFILE
-HTTP Authentification user file
-.It Ev RZ_LOGCOLORS
-Should the log output use colors
-.It Ev RZ_LOGFILE
-Logging output filename/path
-.It Ev RZ_LOGLEVEL
-Target log level/severity
-(0:DEBUG, 1:VERBOSE, 2:INFO, 3:WARN, 4:ERROR, 5:FATAL)
-.It Ev RZ_LOGSHOWSOURCES
-Should the log output contain src info (filename:lineno)
-.It Ev RZ_PIPE_IN
-rzpipe cmd input (file descriptor)
-.It Ev RZ_PIPE_OUT
-rzpipe cmd output (file descriptor)
-.It Ev RZ_PREFIX
-Default prefix rizin was compiled for
-.It Ev RZ_RCFILE
-User config file
-.It Ev SFLIBPATH
-SFLib syscall library path
-.El
-.Sh EXAMPLES
-Start rizin in analysis mode
-.Pq Fl A
-on the /bin/ls executable:
+.Pp
+ANSICON: ansicon's W & H of the buffer and w & h of the window in the form of: "WxH (wxh)"
+.Pp
+DEBUGINFOD_URLS: e bin.dbginfo.debuginfod_urls - use alternative debuginfod server
+.Pp
+COLUMNS: terminal columns to use
+.Pp
+RZ_ABORTLEVEL: target log level/severity when to abort (0:DEBUG, 1:VERBOSE, 2:INFO, 3:WARN, 4:ERROR, 5:FATAL)
+.Pp
+RZ_CURL: whether to use curl (for SSL support)
+.Pp
+RZ_DEBUG_ASSERT: set a breakpoint when hitting an assert
+.Pp
+RZ_DEBUG_TOOL: debug tool to use when showing error messages and crash signal
+.Pp
+RZ_DYLDCACHE_FILTER: dyld cache filter (MacOS dynamic libraries location(s) at runtime)
+.Pp
+RZ_HTTP_AUTHFILE: HTTP Authentification user file
+.Pp
+RZ_LOGCOLORS: should the log output use colors (TODO)
+.Pp
+RZ_LOGFILE: logging output filename/path
+.Pp
+RZ_LOGLEVEL: target log level/severity (0:DEBUG, 1:VERBOSE, 2:INFO, 3:WARN, 4:ERROR, 5:FATAL)
+.Pp
+RZ_LOGSHOWSOURCES: should the log output contain src info (filename:lineno)
+.Pp
+RZ_PIPE_IN: rzpipe cmd input (file descriptor)
+.Pp
+RZ_PIPE_OUT: rzpipe cmd output (file descriptor)
+.Pp
+RZ_PREFIX: default prefix rizin was compiled for
+.Pp
+RZ_RCFILE: user config file
+.Pp
+SFLIBPATH: SFLib syscall library path
+.Sh EXAMPLE
+.Pp
+Start rizin in analysis mode (-A) on the /bin/ls executable:
 .Pp
 .Nm rizin Fl A Ar /bin/ls
 .Pp
@@ -177,15 +172,16 @@ Start rizin's debugger (-d) on /bin/ls and pass arguments
 .Pp
 .Nm rizin Fl d Ar /bin/ls Fl l Ar /tmp
 .Sh SEE ALSO
-.Xr rz-asm 1 ,
-.Xr rz-ax 1 ,
-.Xr rz-bin 1 ,
-.Xr rz-diff 1 ,
-.Xr rz-find 1 ,
-.Xr rz-gg 1 ,
-.Xr rz-hash 1 ,
-.Xr rz-run 1 ,
-.Xr rz-test 1
+.Xr rz-test(1) ,
+.Xr rz-hash(1) ,
+.Xr rz-find(1) ,
+.Xr rz-bin(1) ,
+.Xr rz-diff(1) ,
+.Xr rz-asm(1) ,
+.Xr rz-ax(1) ,
+.Xr rz-gg(1) ,
+.Xr rz-run(1)
 .Sh AUTHORS
-.An pancake Aq Mt [email protected]
-.An byteninjaa0
+pancake <[email protected]>
+.It
+byteninjaa0

binrz/man/rz-asm.1

@@ -1,4 +1,4 @@
-.Dd Jan 22, 2024
+.Dd Dec 29, 2025
 .Dt RZ_ASM 1
 .Sh NAME
 .Nm rz-asm
@@ -22,7 +22,9 @@
 .Sh DESCRIPTION
 This command is part of the Rizin project.
 .Pp
-This tool uses RzAsm to assemble and disassemble files or hexpair strings. It supports a large list of architectures which can be listed using the \-L flag.
+This tool uses RzAsm to assemble and disassemble files or hexpair strings. It supports a large list of architectures which can be listed using the
+.Fl L
+flag.
 .Pp
 .Bl -tag -width Fl
 .It Fl a Ar arch
@@ -82,9 +84,8 @@ Use hex dwords instead of hex pairs when assembling
 .It Fl w
 Describe opcode
 .El
-.Sh Directives
-.Pp
-.Bl -tag -width
+.Sh DIRECTIVES
+.Bl -tag -width ".Ic .fill Ar repeat,size,value"
 .It Ic .intel_syntax
 Use Intel syntax rather than AT&T
 .It Ic .att_syntax
@@ -141,41 +142,43 @@ Mark the start of the text section
 Set the Thumb mode (as opposed to ARM) for ARM architecture
 .El
 .Sh ENVIRONMENT
-.Pp
-RZ_ARCH:      e asm.arch - architecture to assemble/disassemble (same as rz-asm -a)
-.Pp
-RZ_ASM_ARCH:  architecture to assemble/disassemble (same as rz-asm -a)
-.Pp
-RZ_ASM_BITS:  cpu register size (8, 16, 32, 64) (same as rz-asm -b)
-.Pp
-RZ_BITS:      e asm.bits - cpu register size (8, 16, 32, 64) (same as rz-asm -b)
-.Pp
-RZ_DEBUG:     if defined, show error messages and crash signal\n"
-.Pp
-RZ_NOPLUGINS: do not load shared plugins (speedup loading)\n"
-
-
+.Bl -tag -width "RZ_NOPLUGINS"
+.It Ev RZ_ARCH
+Equivalent to
+.Ic e asm.arch
+in rizin. Architecture to assemble/disassemble (same as rz-asm -a).
+.It Ev RZ_ASM_ARCH
+Architecture to assemble/disassemble (same as rz-asm -a).
+.It Ev RZ_ASM_BITS
+CPU register size (8, 16, 32, 64) (same as rz-asm -b).
+.It Ev RZ_BITS
+Equivalent to
+.Ic e asm.bits
+in rizin. CPU register size (8, 16, 32, 64) (same as rz-asm -b).
+.It Ev RZ_DEBUG
+If defined, show error messages and crash signal.
+.It Ev RZ_NOPLUGINS
+Do not load shared plugins to speed up loading.
+.El
 .Sh EXAMPLES
 .Pp
 Assemble opcode:
 .Pp
-.Nm rz-asm Fl a Cm x86 Fl b Cm 32 Ar 'mov eax, 33'
+.Dl $ rz-asm -a x86 -b 32 'mov eax, 33'
 .Pp
 Disassemble opcode:
 .Pp
-.Nm rz-asm Fl d Cm 90
+.Dl $ rz-asm -d 90
 .Sh SEE ALSO
-.Pp
-.Xr rizin(1) ,
-.Xr rz-find(1) ,
-.Xr rz-hash(1) ,
-.Xr rz-bin(1) ,
-.Xr rz-diff(1) ,
-.Xr rz-gg(1) ,
-.Xr rz-run(1) ,
-.Xr rz-ax(1) ,
+.Xr rizin 1 ,
+.Xr rz-find 1 ,
+.Xr rz-hash 1 ,
+.Xr rz-bin 1 ,
+.Xr rz-diff 1 ,
+.Xr rz-gg 1 ,
+.Xr rz-run 1 ,
+.Xr rz-ax 1
 .Sh AUTHORS
-.Pp
 pancake <[email protected]>
-.Pp
-byteninjaa0
+.br
+byteninjaa0

librz/arch/hint.c

@@ -198,8 +198,8 @@ static RzAnalysisRangedHintRecordBase *ensure_ranged_hint_record(RBTree *tree, u
 
 RZ_API void rz_analysis_hint_set_offset(RzAnalysis *a, ut64 addr, const char *typeoff) {
 	SET_HINT(RZ_ANALYSIS_ADDR_HINT_TYPE_TYPE_OFFSET,
-		free(r->type_offset);
-		r->type_offset = rz_str_dup(typeoff););
+		 free(r->type_offset);
+		 r->type_offset = rz_str_dup(typeoff););
 }
 
 RZ_API void rz_analysis_hint_set_nword(RzAnalysis *a, ut64 addr, int nword) {
@@ -240,20 +240,20 @@ RZ_API void rz_analysis_hint_set_ret(RzAnalysis *a, ut64 addr, ut64 val) {
 
 RZ_API void rz_analysis_hint_set_syntax(RzAnalysis *a, ut64 addr, const char *syn) {
 	SET_HINT(RZ_ANALYSIS_ADDR_HINT_TYPE_SYNTAX,
-		free(r->syntax);
-		r->syntax = rz_str_dup(syn););
+		 free(r->syntax);
+		 r->syntax = rz_str_dup(syn););
 }
 
 RZ_API void rz_analysis_hint_set_opcode(RzAnalysis *a, ut64 addr, const char *opcode) {
 	SET_HINT(RZ_ANALYSIS_ADDR_HINT_TYPE_OPCODE,
-		free(r->opcode);
-		r->opcode = rz_str_dup(opcode););
+		 free(r->opcode);
+		 r->opcode = rz_str_dup(opcode););
 }
 
 RZ_API void rz_analysis_hint_set_esil(RzAnalysis *a, ut64 addr, const char *esil) {
 	SET_HINT(RZ_ANALYSIS_ADDR_HINT_TYPE_ESIL,
-		free(r->esil);
-		r->esil = rz_str_dup(esil););
+		 free(r->esil);
+		 r->esil = rz_str_dup(esil););
 }
 
 RZ_API void rz_analysis_hint_set_type(RzAnalysis *a, ut64 addr, int type) {

librz/arch/isa/avr/avr_esil.c

@@ -52,8 +52,8 @@ static OPCODE_DESC *avr_op_analyze(RzAnalysis *analysis, RzAnalysisOp *op, ut64
 #define CPU_MODEL_DECL(model, pc, consts) \
 	{ \
 		model, \
-		pc, \
-		consts \
+			pc, \
+			consts \
 	}
 #define MASK(bits)       ((bits) == 32 ? 0xffffffff : (~((~((ut32)0)) << (bits))))
 #define CPU_PC_MASK(cpu) MASK((cpu)->pc)

librz/arch/isa/avr/avr_il.c

@@ -2219,7 +2219,7 @@ static RzILOpEffect *avr_il_neg(AVROp *aop, AVROp *next_op, ut64 pc, RzAnalysis
 
 static RzILOpEffect *avr_il_or(AVROp *aop, AVROp *next_op, ut64 pc, RzAnalysis *analysis) {
 	RzILOpPure *x, *y;
-	RzILOpEffect *or, *S, *V, *N, *Z;
+	RzILOpEffect * or, *S, *V, *N, *Z;
 	// Rd = Rd | Rr
 	// changes S|V|N|Z
 	ut16 Rd = aop->param[0];
@@ -2252,7 +2252,7 @@ static RzILOpEffect *avr_il_or(AVROp *aop, AVROp *next_op, ut64 pc, RzAnalysis *
 
 static RzILOpEffect *avr_il_ori(AVROp *aop, AVROp *next_op, ut64 pc, RzAnalysis *analysis) {
 	RzILOpPure *x, *y;
-	RzILOpEffect *or, *S, *V, *N, *Z;
+	RzILOpEffect * or, *S, *V, *N, *Z;
 	// Rd = Rd | K
 	// changes S|V|N|Z
 	ut16 Rd = aop->param[0];

librz/arch/isa/mips/il/common.c

@@ -139,7 +139,7 @@ static RzILOpEffect *mips_il_align(const csh *handle, const cs_insn *insn, const
 	RzILOpPure *bp_8 = UN(32, IMM(3) << 3); // bp * 8
 	RzILOpPure *gprlen_bp_8 = UN(32, IMM(3) << 3); // gprlen - (bp * 8)
 
-	RzILOpPure *or = LOGOR(SHIFTL0(rt, bp_8), SHIFTR0(rs, gprlen_bp_8));
+	RzILOpPure * or = LOGOR(SHIFTL0(rt, bp_8), SHIFTR0(rs, gprlen_bp_8));
 	if (gprlen > 32) {
 		or = SIGNED(gprlen, or);
 	}
@@ -157,7 +157,7 @@ static RzILOpEffect *mips_il_dalign(const csh *handle, const cs_insn *insn, cons
 	RzILOpPure *bp_8 = UN(gprlen, IMM(3) << 3); // bp * 8
 	RzILOpPure *gprlen_bp_8 = UN(gprlen, IMM(3) << 3); // gprlen - (bp * 8)
 
-	RzILOpPure *or = LOGOR(SHIFTL0(rt, bp_8), SHIFTR0(rs, gprlen_bp_8));
+	RzILOpPure * or = LOGOR(SHIFTL0(rt, bp_8), SHIFTR0(rs, gprlen_bp_8));
 	return SETG(rd, or);
 }
 

librz/arch/isa/rx/rx_opcode_detail.c

@@ -33,10 +33,10 @@
 	{ .type = RX_TOKEN_CB, .tk.cb.tk_len = (x) }
 #define RxDspSplit(x, v, it, xx) \
 	{ .type = RX_TOKEN_DSP_SPLIT, \
-		.tk.dsp_sp.tk_len = (x), \
-		.tk.dsp_sp.vid = (v), \
-		.tk.dsp_sp.tk_len_more = (xx), \
-		.tk.dsp_sp.interval = (it) }
+	  .tk.dsp_sp.tk_len = (x), \
+	  .tk.dsp_sp.vid = (v), \
+	  .tk.dsp_sp.tk_len_more = (xx), \
+	  .tk.dsp_sp.interval = (it) }
 #define RxIgnore(x) \
 	{ .type = RX_TOKEN_IGNORE, .tk.reserved.tk_len = (x) }
 

librz/arch/isa/sh/sh_il.c

@@ -515,10 +515,10 @@ static RzILOpBool *sh_il_is_add_carry(RZ_OWN RzILOpPure *res, RZ_OWN RzILOpPure
 	RzILOpBool *xr = AND(DUP(xmsb), DUP(nres));
 
 	// bit = xy | ry | xr
-	RzILOpBool *or = OR(xy, ry);
+	RzILOpBool * or = OR(xy, ry);
 	or = OR(or, xr);
 
-	return or;
+	return or ;
 }
 
 /**
@@ -550,10 +550,10 @@ static RzILOpBool *sh_il_is_sub_borrow(RZ_OWN RzILOpPure *res, RZ_OWN RzILOpPure
 	RzILOpBool *rnx = AND(DUP(resmsb), DUP(nx));
 
 	// bit = nxy | rny | rnx
-	RzILOpBool *or = OR(nxy, rny);
+	RzILOpBool * or = OR(nxy, rny);
 	or = OR(or, rnx);
 
-	return or;
+	return or ;
 }
 
 /**
@@ -579,9 +579,9 @@ static RzILOpBool *sh_il_is_add_overflow(RZ_OWN RzILOpPure *res, RZ_OWN RzILOpPu
 	// res & !x & !y
 	RzILOpBool *rnxny = AND(AND(DUP(resmsb), INV(DUP(xmsb))), INV(DUP(ymsb)));
 	// or = nrxy | rnxny
-	RzILOpBool *or = OR(nrxy, rnxny);
+	RzILOpBool * or = OR(nrxy, rnxny);
 
-	return or;
+	return or ;
 }
 
 /**
@@ -607,9 +607,9 @@ static RzILOpBool *sh_il_is_sub_underflow(RZ_OWN RzILOpPure *res, RZ_OWN RzILOpP
 	// res & !x & y
 	RzILOpBool *rnxy = AND(AND(DUP(resmsb), INV(DUP(xmsb))), DUP(ymsb));
 	// or = nrxny | rnxy
-	RzILOpBool *or = OR(nrxny, rnxy);
+	RzILOpBool * or = OR(nrxny, rnxy);
 
-	return or;
+	return or ;
 }
 
 /* Instruction implementations */