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Add missing newlines to register definitions.
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210 files changed

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aarch32-cpu/src/register/actlr.rs

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@@ -7,22 +7,27 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
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pub struct Actlr(pub u32);
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impl SysReg for Actlr {
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const CP: u32 = 15;
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const CRN: u32 = 1;
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const OP1: u32 = 0;
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const CRM: u32 = 0;
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const OP2: u32 = 1;
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}
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impl crate::register::SysRegRead for Actlr {}
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impl Actlr {
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#[inline]
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/// Reads ACTLR (*Auxiliary Control Register*)
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pub fn read() -> Actlr {
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unsafe { Self(<Self as SysRegRead>::read_raw()) }
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}
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}
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impl crate::register::SysRegWrite for Actlr {}
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impl Actlr {
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#[inline]
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/// Writes ACTLR (*Auxiliary Control Register*)

aarch32-cpu/src/register/actlr2.rs

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@@ -7,22 +7,27 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
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pub struct Actlr2(pub u32);
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impl SysReg for Actlr2 {
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const CP: u32 = 15;
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const CRN: u32 = 1;
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const OP1: u32 = 0;
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const CRM: u32 = 0;
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const OP2: u32 = 3;
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}
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impl crate::register::SysRegRead for Actlr2 {}
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impl Actlr2 {
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#[inline]
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/// Reads ACTLR2 (*Auxiliary Control Register 2*)
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pub fn read() -> Actlr2 {
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unsafe { Self(<Self as SysRegRead>::read_raw()) }
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}
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}
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impl crate::register::SysRegWrite for Actlr2 {}
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impl Actlr2 {
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#[inline]
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/// Writes ACTLR2 (*Auxiliary Control Register 2*)

aarch32-cpu/src/register/adfsr.rs

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Original file line numberDiff line numberDiff line change
@@ -7,22 +7,27 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
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pub struct Adfsr(pub u32);
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impl SysReg for Adfsr {
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const CP: u32 = 15;
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const CRN: u32 = 5;
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const OP1: u32 = 0;
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const CRM: u32 = 1;
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const OP2: u32 = 0;
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}
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impl crate::register::SysRegRead for Adfsr {}
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impl Adfsr {
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#[inline]
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/// Reads ADFSR (*Auxiliary Data Fault Status Register*)
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pub fn read() -> Adfsr {
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unsafe { Self(<Self as SysRegRead>::read_raw()) }
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}
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}
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impl crate::register::SysRegWrite for Adfsr {}
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impl Adfsr {
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#[inline]
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/// Writes ADFSR (*Auxiliary Data Fault Status Register*)

aarch32-cpu/src/register/aidr.rs

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@@ -7,14 +7,17 @@ use crate::register::{SysReg, SysRegRead};
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
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pub struct Aidr(pub u32);
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impl SysReg for Aidr {
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const CP: u32 = 15;
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const CRN: u32 = 0;
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const OP1: u32 = 1;
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const CRM: u32 = 0;
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const OP2: u32 = 7;
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}
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impl crate::register::SysRegRead for Aidr {}
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impl Aidr {
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#[inline]
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/// Reads AIDR (*Auxiliary ID Register*)

aarch32-cpu/src/register/aifsr.rs

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@@ -7,22 +7,27 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
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pub struct Aifsr(pub u32);
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impl SysReg for Aifsr {
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const CP: u32 = 15;
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const CRN: u32 = 5;
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const OP1: u32 = 0;
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const CRM: u32 = 1;
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const OP2: u32 = 1;
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}
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impl crate::register::SysRegRead for Aifsr {}
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impl Aifsr {
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#[inline]
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/// Reads AIFSR (*Auxiliary Instruction Fault Status Register*)
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pub fn read() -> Aifsr {
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unsafe { Self(<Self as SysRegRead>::read_raw()) }
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}
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}
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impl crate::register::SysRegWrite for Aifsr {}
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impl Aifsr {
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#[inline]
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/// Writes AIFSR (*Auxiliary Instruction Fault Status Register*)

aarch32-cpu/src/register/amair0.rs

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@@ -7,22 +7,27 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
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pub struct Amair0(pub u32);
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impl SysReg for Amair0 {
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const CP: u32 = 15;
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const CRN: u32 = 10;
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const OP1: u32 = 0;
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const CRM: u32 = 3;
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const OP2: u32 = 0;
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}
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impl crate::register::SysRegRead for Amair0 {}
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impl Amair0 {
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#[inline]
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/// Reads AMAIR0 (*Auxiliary Memory Attribute Indirection Register 0*)
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pub fn read() -> Amair0 {
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unsafe { Self(<Self as SysRegRead>::read_raw()) }
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}
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}
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impl crate::register::SysRegWrite for Amair0 {}
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impl Amair0 {
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#[inline]
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/// Writes AMAIR0 (*Auxiliary Memory Attribute Indirection Register 0*)

aarch32-cpu/src/register/amair1.rs

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@@ -7,22 +7,27 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
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pub struct Amair1(pub u32);
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impl SysReg for Amair1 {
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const CP: u32 = 15;
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const CRN: u32 = 10;
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const OP1: u32 = 0;
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const CRM: u32 = 3;
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const OP2: u32 = 1;
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}
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impl crate::register::SysRegRead for Amair1 {}
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impl Amair1 {
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#[inline]
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/// Reads AMAIR1 (*Auxiliary Memory Attribute Indirection Register 1*)
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pub fn read() -> Amair1 {
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unsafe { Self(<Self as SysRegRead>::read_raw()) }
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}
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}
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impl crate::register::SysRegWrite for Amair1 {}
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impl Amair1 {
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#[inline]
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/// Writes AMAIR1 (*Auxiliary Memory Attribute Indirection Register 1*)

aarch32-cpu/src/register/armv8r/cntfrq.rs

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@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
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pub struct Cntfrq(pub u32);
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impl SysReg for Cntfrq {
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const CP: u32 = 15;
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const CRN: u32 = 14;

aarch32-cpu/src/register/armv8r/cntp_ctl.rs

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@@ -37,6 +37,7 @@ impl SysReg for CntpCtl {
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const CRM: u32 = 2;
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const OP2: u32 = 1;
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}
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impl SysRegRead for CntpCtl {}
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impl CntpCtl {

aarch32-cpu/src/register/armv8r/cntp_tval.rs

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@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
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pub struct CntpTval(pub u32);
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impl SysReg for CntpTval {
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const CP: u32 = 15;
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const CRN: u32 = 14;

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